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ARM: NOMMU: Introduce dma operations for noMMU
R/M classes of cpus can have memory covered by MPU which in turn might configure RAM as Normal i.e. bufferable and cacheable. It breaks dma_alloc_coherent() and friends, since data can stuck in caches now or be buffered. This patch factors out DMA support for NOMMU configuration into separate entity which provides dedicated dma_ops. We have to handle there several cases: - configurations with MMU/MPU setup - configurations without MMU/MPU setup - special case for M-class, since caches and MPU there are optional In general we rely on default DMA area for coherent allocations or/and per-device memory reserves suitable for coherent DMA, so if such regions are set coherent allocations go from there. In case MMU/MPU was not setup we fallback to normal page allocator for DMA memory allocation. In case we run M-class cpus, for configuration without cache support (like Cortex-M3/M4) dma operations are forced to be coherent and wired with dma-noop (such decision is made based on cacheid global variable); however, if caches are detected there and no DMA coherent region is given (either default or per-device), dma is disallowed even MPU is not set - it is because M-class implement system memory map which defines part of address space as Normal memory. Reported-by: Alexandre Torgue <alexandre.torgue@st.com> Reported-by: Andras Szemzo <sza@esh.hu> Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> [hch: removed the dma_supported() implementation that isn't required anymore] Signed-off-by: Christoph Hellwig <hch@lst.de>
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07c75d7a6b
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@ -22,6 +22,7 @@ config ARM
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select CLONE_BACKWARDS
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select CPU_PM if (SUSPEND || CPU_IDLE)
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select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
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select DMA_NOOP_OPS if !MMU
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select EDAC_SUPPORT
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select EDAC_ATOMIC_SCRUB
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select GENERIC_ALLOCATOR
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@ -17,7 +17,7 @@ extern const struct dma_map_ops arm_coherent_dma_ops;
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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{
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return &arm_dma_ops;
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return IS_ENABLED(CONFIG_MMU) ? &arm_dma_ops : &dma_noop_ops;
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}
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#ifdef __arch_page_to_dma
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@ -2,9 +2,8 @@
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# Makefile for the linux arm-specific parts of the memory manager.
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#
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obj-y := dma-mapping.o extable.o fault.o init.o \
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iomap.o
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obj-y := extable.o fault.o init.o iomap.o
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obj-y += dma-mapping$(MMUEXT).o
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obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
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mmap.o pgd.o mmu.o pageattr.o
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228
arch/arm/mm/dma-mapping-nommu.c
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228
arch/arm/mm/dma-mapping-nommu.c
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@ -0,0 +1,228 @@
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/*
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* Based on linux/arch/arm/mm/dma-mapping.c
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*
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* Copyright (C) 2000-2004 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <asm/cachetype.h>
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#include <asm/cacheflush.h>
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#include <asm/outercache.h>
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#include <asm/cp15.h>
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#include "dma.h"
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/*
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* dma_noop_ops is used if
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* - MMU/MPU is off
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* - cpu is v7m w/o cache support
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* - device is coherent
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* otherwise arm_nommu_dma_ops is used.
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*
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* arm_nommu_dma_ops rely on consistent DMA memory (please, refer to
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* [1] on how to declare such memory).
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*
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* [1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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*/
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static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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unsigned long attrs)
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{
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const struct dma_map_ops *ops = &dma_noop_ops;
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/*
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* We are here because:
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* - no consistent DMA region has been defined, so we can't
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* continue.
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* - there is no space left in consistent DMA region, so we
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* only can fallback to generic allocator if we are
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* advertised that consistency is not required.
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*/
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if (attrs & DMA_ATTR_NON_CONSISTENT)
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return ops->alloc(dev, size, dma_handle, gfp, attrs);
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WARN_ON_ONCE(1);
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return NULL;
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}
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static void arm_nommu_dma_free(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_addr,
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unsigned long attrs)
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{
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const struct dma_map_ops *ops = &dma_noop_ops;
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if (attrs & DMA_ATTR_NON_CONSISTENT)
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ops->free(dev, size, cpu_addr, dma_addr, attrs);
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else
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WARN_ON_ONCE(1);
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return;
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}
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static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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dmac_map_area(__va(paddr), size, dir);
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if (dir == DMA_FROM_DEVICE)
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outer_inv_range(paddr, paddr + size);
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else
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outer_clean_range(paddr, paddr + size);
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}
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static void __dma_page_dev_to_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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if (dir != DMA_TO_DEVICE) {
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outer_inv_range(paddr, paddr + size);
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dmac_unmap_area(__va(paddr), size, dir);
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}
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}
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static dma_addr_t arm_nommu_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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dma_addr_t handle = page_to_phys(page) + offset;
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__dma_page_cpu_to_dev(handle, size, dir);
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return handle;
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}
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static void arm_nommu_dma_unmap_page(struct device *dev, dma_addr_t handle,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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__dma_page_dev_to_cpu(handle, size, dir);
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}
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static int arm_nommu_dma_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sgl, sg, nents, i) {
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sg_dma_address(sg) = sg_phys(sg);
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sg_dma_len(sg) = sg->length;
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__dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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return nents;
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}
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static void arm_nommu_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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static void arm_nommu_dma_sync_single_for_device(struct device *dev,
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dma_addr_t handle, size_t size, enum dma_data_direction dir)
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{
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__dma_page_cpu_to_dev(handle, size, dir);
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}
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static void arm_nommu_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t handle, size_t size, enum dma_data_direction dir)
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{
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__dma_page_cpu_to_dev(handle, size, dir);
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}
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static void arm_nommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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const struct dma_map_ops arm_nommu_dma_ops = {
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.alloc = arm_nommu_dma_alloc,
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.free = arm_nommu_dma_free,
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.map_page = arm_nommu_dma_map_page,
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.unmap_page = arm_nommu_dma_unmap_page,
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.map_sg = arm_nommu_dma_map_sg,
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.unmap_sg = arm_nommu_dma_unmap_sg,
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.sync_single_for_device = arm_nommu_dma_sync_single_for_device,
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.sync_single_for_cpu = arm_nommu_dma_sync_single_for_cpu,
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.sync_sg_for_device = arm_nommu_dma_sync_sg_for_device,
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.sync_sg_for_cpu = arm_nommu_dma_sync_sg_for_cpu,
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};
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EXPORT_SYMBOL(arm_nommu_dma_ops);
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static const struct dma_map_ops *arm_nommu_get_dma_map_ops(bool coherent)
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{
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return coherent ? &dma_noop_ops : &arm_nommu_dma_ops;
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}
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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const struct dma_map_ops *dma_ops;
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if (IS_ENABLED(CONFIG_CPU_V7M)) {
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/*
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* Cache support for v7m is optional, so can be treated as
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* coherent if no cache has been detected. Note that it is not
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* enough to check if MPU is in use or not since in absense of
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* MPU system memory map is used.
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*/
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dev->archdata.dma_coherent = (cacheid) ? coherent : true;
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} else {
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/*
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* Assume coherent DMA in case MMU/MPU has not been set up.
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*/
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dev->archdata.dma_coherent = (get_cr() & CR_M) ? coherent : true;
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}
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dma_ops = arm_nommu_get_dma_map_ops(dev->archdata.dma_coherent);
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set_dma_ops(dev, dma_ops);
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}
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void arch_teardown_dma_ops(struct device *dev)
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{
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}
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#define PREALLOC_DMA_DEBUG_ENTRIES 4096
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static int __init dma_debug_do_init(void)
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{
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dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
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return 0;
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}
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core_initcall(dma_debug_do_init);
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