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ASoC: mediatek: mt8365: Add DMIC DAI support
Add Digital Micro Device Audio Interface support for MT8365 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://patch.msgid.link/20240226-audio-i350-v7-8-6518d953a141@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Alexandre Mergnat
Mark Brown
parent
7c58c88e52
commit
1c50ec75ce
340
sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
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340
sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
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@ -0,0 +1,340 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek 8365 ALSA SoC Audio DAI DMIC Control
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*
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* Copyright (c) 2024 MediaTek Inc.
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* Authors: Jia Zeng <jia.zeng@mediatek.com>
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* Alexandre Mergnat <amergnat@baylibre.com>
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*/
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include "mt8365-afe-clk.h"
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#include "mt8365-afe-common.h"
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struct mt8365_dmic_data {
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bool two_wire_mode;
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unsigned int clk_phase_sel_ch1;
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unsigned int clk_phase_sel_ch2;
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bool iir_on;
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unsigned int irr_mode;
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unsigned int dmic_mode;
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unsigned int dmic_channel;
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};
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static int get_chan_reg(unsigned int channel)
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{
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switch (channel) {
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case 8:
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fallthrough;
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case 7:
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return AFE_DMIC3_UL_SRC_CON0;
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case 6:
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fallthrough;
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case 5:
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return AFE_DMIC2_UL_SRC_CON0;
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case 4:
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fallthrough;
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case 3:
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return AFE_DMIC1_UL_SRC_CON0;
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case 2:
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fallthrough;
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case 1:
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return AFE_DMIC0_UL_SRC_CON0;
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default:
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return -EINVAL;
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}
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}
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/* DAI Drivers */
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static void audio_dmic_adda_enable(struct mtk_base_afe *afe)
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{
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mt8365_dai_enable_adda_on(afe);
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regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0,
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AFE_ADDA_UL_DL_DMIC_CLKDIV_ON,
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AFE_ADDA_UL_DL_DMIC_CLKDIV_ON);
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}
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static void audio_dmic_adda_disable(struct mtk_base_afe *afe)
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{
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regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0,
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AFE_ADDA_UL_DL_DMIC_CLKDIV_ON,
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~AFE_ADDA_UL_DL_DMIC_CLKDIV_ON);
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mt8365_dai_disable_adda_on(afe);
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}
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static void mt8365_dai_enable_dmic(struct mtk_base_afe *afe,
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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struct mt8365_dmic_data *dmic_data = afe_priv->dai_priv[MT8365_AFE_IO_DMIC];
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unsigned int val_mask;
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int reg = get_chan_reg(dmic_data->dmic_channel);
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if (reg < 0)
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return;
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/* val and mask will be always same to enable */
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val_mask = DMIC_TOP_CON_CH1_ON |
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DMIC_TOP_CON_CH2_ON |
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DMIC_TOP_CON_SRC_ON;
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regmap_update_bits(afe->regmap, reg, val_mask, val_mask);
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}
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static void mt8365_dai_disable_dmic(struct mtk_base_afe *afe,
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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struct mt8365_dmic_data *dmic_data = afe_priv->dai_priv[MT8365_AFE_IO_DMIC];
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unsigned int mask;
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int reg = get_chan_reg(dmic_data->dmic_channel);
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if (reg < 0)
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return;
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dev_dbg(afe->dev, "%s dmic_channel %d\n", __func__, dmic_data->dmic_channel);
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mask = DMIC_TOP_CON_CH1_ON |
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DMIC_TOP_CON_CH2_ON |
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DMIC_TOP_CON_SRC_ON |
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DMIC_TOP_CON_SDM3_LEVEL_MODE;
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/* Set all masked values to 0 */
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regmap_update_bits(afe->regmap, reg, mask, 0);
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}
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static const struct reg_sequence mt8365_dmic_iir_coeff[] = {
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{ AFE_DMIC0_IIR_COEF_02_01, 0x00000000 },
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{ AFE_DMIC0_IIR_COEF_04_03, 0x00003FB8 },
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{ AFE_DMIC0_IIR_COEF_06_05, 0x3FB80000 },
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{ AFE_DMIC0_IIR_COEF_08_07, 0x3FB80000 },
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{ AFE_DMIC0_IIR_COEF_10_09, 0x0000C048 },
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{ AFE_DMIC1_IIR_COEF_02_01, 0x00000000 },
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{ AFE_DMIC1_IIR_COEF_04_03, 0x00003FB8 },
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{ AFE_DMIC1_IIR_COEF_06_05, 0x3FB80000 },
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{ AFE_DMIC1_IIR_COEF_08_07, 0x3FB80000 },
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{ AFE_DMIC1_IIR_COEF_10_09, 0x0000C048 },
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{ AFE_DMIC2_IIR_COEF_02_01, 0x00000000 },
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{ AFE_DMIC2_IIR_COEF_04_03, 0x00003FB8 },
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{ AFE_DMIC2_IIR_COEF_06_05, 0x3FB80000 },
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{ AFE_DMIC2_IIR_COEF_08_07, 0x3FB80000 },
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{ AFE_DMIC2_IIR_COEF_10_09, 0x0000C048 },
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{ AFE_DMIC3_IIR_COEF_02_01, 0x00000000 },
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{ AFE_DMIC3_IIR_COEF_04_03, 0x00003FB8 },
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{ AFE_DMIC3_IIR_COEF_06_05, 0x3FB80000 },
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{ AFE_DMIC3_IIR_COEF_08_07, 0x3FB80000 },
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{ AFE_DMIC3_IIR_COEF_10_09, 0x0000C048 },
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};
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static int mt8365_dai_load_dmic_iir_coeff_table(struct mtk_base_afe *afe)
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{
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return regmap_multi_reg_write(afe->regmap,
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mt8365_dmic_iir_coeff,
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ARRAY_SIZE(mt8365_dmic_iir_coeff));
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}
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static int mt8365_dai_configure_dmic(struct mtk_base_afe *afe,
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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struct mt8365_dmic_data *dmic_data = afe_priv->dai_priv[MT8365_AFE_IO_DMIC];
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bool two_wire_mode = dmic_data->two_wire_mode;
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unsigned int clk_phase_sel_ch1 = dmic_data->clk_phase_sel_ch1;
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unsigned int clk_phase_sel_ch2 = dmic_data->clk_phase_sel_ch2;
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unsigned int val = 0;
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unsigned int rate = dai->rate;
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int reg = get_chan_reg(dai->channels);
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if (reg < 0)
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return -EINVAL;
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dmic_data->dmic_channel = dai->channels;
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val |= DMIC_TOP_CON_SDM3_LEVEL_MODE;
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if (two_wire_mode) {
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val |= DMIC_TOP_CON_TWO_WIRE_MODE;
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} else {
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val |= FIELD_PREP(DMIC_TOP_CON_CK_PHASE_SEL_CH1,
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clk_phase_sel_ch1);
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val |= FIELD_PREP(DMIC_TOP_CON_CK_PHASE_SEL_CH2,
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clk_phase_sel_ch2);
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}
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switch (rate) {
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case 48000:
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val |= DMIC_TOP_CON_VOICE_MODE_48K;
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break;
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case 32000:
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val |= DMIC_TOP_CON_VOICE_MODE_32K;
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break;
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case 16000:
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val |= DMIC_TOP_CON_VOICE_MODE_16K;
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break;
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case 8000:
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val |= DMIC_TOP_CON_VOICE_MODE_8K;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(afe->regmap, reg, DMIC_TOP_CON_CONFIG_MASK, val);
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return 0;
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}
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static int mt8365_dai_dmic_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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mt8365_afe_enable_main_clk(afe);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC0_ADC);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC1_ADC);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC2_ADC);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC3_ADC);
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audio_dmic_adda_enable(afe);
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return 0;
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}
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static void mt8365_dai_dmic_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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mt8365_dai_disable_dmic(afe, substream, dai);
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audio_dmic_adda_disable(afe);
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/* HW Request delay 125us before CG off */
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usleep_range(125, 300);
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mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC3_ADC);
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mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC2_ADC);
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mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC1_ADC);
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mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC0_ADC);
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mt8365_afe_disable_main_clk(afe);
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}
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static int mt8365_dai_dmic_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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mt8365_dai_configure_dmic(afe, substream, dai);
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mt8365_dai_enable_dmic(afe, substream, dai);
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return 0;
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}
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static const struct snd_soc_dai_ops mt8365_afe_dmic_ops = {
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.startup = mt8365_dai_dmic_startup,
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.shutdown = mt8365_dai_dmic_shutdown,
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.prepare = mt8365_dai_dmic_prepare,
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};
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static struct snd_soc_dai_driver mtk_dai_dmic_driver[] = {
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{
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.name = "DMIC",
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.id = MT8365_AFE_IO_DMIC,
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.capture = {
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.stream_name = "DMIC Capture",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_16000 |
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SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.ops = &mt8365_afe_dmic_ops,
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}
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};
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/* DAI Controls */
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/* Values for 48kHz mode */
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static const char * const iir_mode_src[] = {
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"SW custom", "5Hz", "10Hz", "25Hz", "50Hz", "65Hz"
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};
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static SOC_ENUM_SINGLE_DECL(iir_mode, AFE_DMIC0_UL_SRC_CON0, 7, iir_mode_src);
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static const struct snd_kcontrol_new mtk_dai_dmic_controls[] = {
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SOC_SINGLE("DMIC IIR Switch", AFE_DMIC0_UL_SRC_CON0, DMIC_TOP_CON_IIR_ON, 1, 0),
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SOC_ENUM("DMIC IIR Mode", iir_mode),
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};
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/* DAI widget */
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static const struct snd_soc_dapm_widget mtk_dai_dmic_widgets[] = {
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SND_SOC_DAPM_INPUT("DMIC In"),
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};
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/* DAI route */
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static const struct snd_soc_dapm_route mtk_dai_dmic_routes[] = {
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{"I14", NULL, "DMIC Capture"},
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{"I15", NULL, "DMIC Capture"},
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{"I16", NULL, "DMIC Capture"},
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{"I17", NULL, "DMIC Capture"},
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{"I18", NULL, "DMIC Capture"},
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{"I19", NULL, "DMIC Capture"},
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{"I20", NULL, "DMIC Capture"},
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{"I21", NULL, "DMIC Capture"},
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{"DMIC Capture", NULL, "DMIC In"},
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};
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static int init_dmic_priv_data(struct mtk_base_afe *afe)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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struct mt8365_dmic_data *dmic_priv;
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struct device_node *np = afe->dev->of_node;
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unsigned int temps[4];
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int ret;
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dmic_priv = devm_kzalloc(afe->dev, sizeof(*dmic_priv), GFP_KERNEL);
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if (!dmic_priv)
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return -ENOMEM;
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ret = of_property_read_u32_array(np, "mediatek,dmic-mode",
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&temps[0],
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1);
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if (ret == 0)
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dmic_priv->two_wire_mode = !!temps[0];
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if (!dmic_priv->two_wire_mode) {
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dmic_priv->clk_phase_sel_ch1 = 0;
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dmic_priv->clk_phase_sel_ch2 = 4;
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}
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afe_priv->dai_priv[MT8365_AFE_IO_DMIC] = dmic_priv;
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return 0;
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}
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int mt8365_dai_dmic_register(struct mtk_base_afe *afe)
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{
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struct mtk_base_afe_dai *dai;
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dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
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if (!dai)
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return -ENOMEM;
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list_add(&dai->list, &afe->sub_dais);
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dai->dai_drivers = mtk_dai_dmic_driver;
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dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_dmic_driver);
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dai->controls = mtk_dai_dmic_controls;
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dai->num_controls = ARRAY_SIZE(mtk_dai_dmic_controls);
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dai->dapm_widgets = mtk_dai_dmic_widgets;
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dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_dmic_widgets);
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dai->dapm_routes = mtk_dai_dmic_routes;
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dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_dmic_routes);
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return init_dmic_priv_data(afe);
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}
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