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ACPICA: IORT: Update for revision E.f
ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory Access Flag field in the Memory Access Properties table, mainly for a PCI Root Complex. This CANWBS defines the coherency of memory accesses to be not marked IOWB cacheable/shareable. Its value further implies the coherency impact from a pair of mismatched memory attributes (e.g. in a nested translation case): 0x0: Use of mismatched memory attributes for accesses made by this device may lead to a loss of coherency. 0x1: Coherency of accesses made by this device to locations in Conventional memory are ensured as follows, even if the memory attributes for the accesses presented by the device or provided by the SMMU are different from Inner and Outer Write-back cacheable, Shareable. Link: https://github.com/acpica/acpica/commit/c4f5c083 Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Acked-by: Hanjun Guo <guohanjun@huawei.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/2-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -453,7 +453,7 @@ struct acpi_table_ccel {
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* IORT - IO Remapping Table
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*
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* Conforms to "IO Remapping Table System Software on ARM Platforms",
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* Document number: ARM DEN 0049E.e, Sep 2022
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* Document number: ARM DEN 0049E.f, Apr 2024
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*
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******************************************************************************/
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@ -524,6 +524,7 @@ struct acpi_iort_memory_access {
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#define ACPI_IORT_MF_COHERENCY (1)
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#define ACPI_IORT_MF_ATTRIBUTES (1<<1)
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#define ACPI_IORT_MF_CANWBS (1<<2)
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/*
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* IORT node specific subtables
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