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ath9k_hw: remove ATH9K_HW_CAP_CST
its not used anywhere in the current code Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -2399,12 +2399,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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else
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pCap->num_gpio_pins = AR_NUM_GPIO;
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if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
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pCap->hw_caps |= ATH9K_HW_CAP_CST;
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if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
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pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
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} else {
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else
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pCap->rts_aggr_limit = (8 * 1024);
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}
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#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
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ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
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@ -196,22 +196,21 @@ enum ath_ini_subsys {
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enum ath9k_hw_caps {
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ATH9K_HW_CAP_HT = BIT(0),
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ATH9K_HW_CAP_RFSILENT = BIT(1),
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ATH9K_HW_CAP_CST = BIT(2),
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ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
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ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
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ATH9K_HW_CAP_EDMA = BIT(6),
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ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
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ATH9K_HW_CAP_LDPC = BIT(8),
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ATH9K_HW_CAP_FASTCLOCK = BIT(9),
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ATH9K_HW_CAP_SGI_20 = BIT(10),
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ATH9K_HW_CAP_PAPRD = BIT(11),
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ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
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ATH9K_HW_CAP_2GHZ = BIT(13),
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ATH9K_HW_CAP_5GHZ = BIT(14),
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ATH9K_HW_CAP_APM = BIT(15),
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ATH9K_HW_CAP_RTT = BIT(16),
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ATH9K_HW_CAP_MCI = BIT(17),
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ATH9K_HW_CAP_DFS = BIT(18),
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ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
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ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
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ATH9K_HW_CAP_EDMA = BIT(4),
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ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
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ATH9K_HW_CAP_LDPC = BIT(6),
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ATH9K_HW_CAP_FASTCLOCK = BIT(7),
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ATH9K_HW_CAP_SGI_20 = BIT(8),
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ATH9K_HW_CAP_PAPRD = BIT(9),
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ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
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ATH9K_HW_CAP_2GHZ = BIT(11),
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ATH9K_HW_CAP_5GHZ = BIT(12),
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ATH9K_HW_CAP_APM = BIT(13),
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ATH9K_HW_CAP_RTT = BIT(14),
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ATH9K_HW_CAP_MCI = BIT(15),
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ATH9K_HW_CAP_DFS = BIT(16),
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};
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struct ath9k_hw_capabilities {
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