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counter: stm32-timer-cnt: add support for capture events
Add support for capture events. Captured counter value for each channel can be retrieved through CCRx register. STM32 timers can have up to 4 capture channels (on input channel 1 to channel 4), hence need to check the number of channels before reading the capture data. The capture configuration is hard-coded to capture signals on both edges (non-inverted). Interrupts are used to report events independently for each channel. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Acked-by: Lee Jones <lee@kernel.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-11-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
This commit is contained in:
Fabrice Gasnier
William Breathitt Gray
parent
2c70ccd459
commit
1aed15275b
@ -262,6 +262,40 @@ static int stm32_count_prescaler_write(struct counter_device *counter,
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return regmap_write(priv->regmap, TIM_PSC, psc);
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}
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static int stm32_count_cap_read(struct counter_device *counter,
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struct counter_count *count,
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size_t ch, u64 *cap)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 ccrx;
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if (ch >= priv->nchannels)
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return -EOPNOTSUPP;
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switch (ch) {
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case 0:
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regmap_read(priv->regmap, TIM_CCR1, &ccrx);
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break;
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case 1:
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regmap_read(priv->regmap, TIM_CCR2, &ccrx);
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break;
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case 2:
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regmap_read(priv->regmap, TIM_CCR3, &ccrx);
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break;
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case 3:
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regmap_read(priv->regmap, TIM_CCR4, &ccrx);
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break;
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default:
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return -EINVAL;
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}
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dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx);
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*cap = ccrx;
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return 0;
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}
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static int stm32_count_nb_ovf_read(struct counter_device *counter,
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struct counter_count *count, u64 *val)
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{
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@ -288,6 +322,8 @@ static int stm32_count_nb_ovf_write(struct counter_device *counter,
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return 0;
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}
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static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4);
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static struct counter_comp stm32_count_ext[] = {
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COUNTER_COMP_DIRECTION(stm32_count_direction_read),
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COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),
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@ -295,6 +331,7 @@ static struct counter_comp stm32_count_ext[] = {
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stm32_count_ceiling_write),
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COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read,
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stm32_count_prescaler_write),
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COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array),
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COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write),
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};
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@ -353,11 +390,68 @@ static int stm32_action_read(struct counter_device *counter,
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}
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}
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struct stm32_count_cc_regs {
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u32 ccmr_reg;
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u32 ccmr_mask;
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u32 ccmr_bits;
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u32 ccer_bits;
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};
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static const struct stm32_count_cc_regs stm32_cc[] = {
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{ TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1,
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TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP },
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{ TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2,
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TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP },
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{ TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3,
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TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP },
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{ TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4,
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TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP },
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};
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static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch,
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bool enable)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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const struct stm32_count_cc_regs *cc;
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u32 ccmr, ccer;
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if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) {
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dev_err(counter->parent, "invalid ch: %d\n", ch);
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return -EINVAL;
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}
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cc = &stm32_cc[ch];
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/*
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* configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2...
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* Select both edges / non-inverted to trigger a capture.
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*/
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if (enable) {
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/* first clear possibly latched capture flag upon enabling */
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if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits))
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regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch));
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regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask,
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cc->ccmr_bits);
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regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits);
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} else {
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regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits);
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regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask);
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}
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regmap_read(priv->regmap, cc->ccmr_reg, &ccmr);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis",
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ch, ccmr, ccer);
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return 0;
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}
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static int stm32_count_events_configure(struct counter_device *counter)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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struct counter_event_node *event_node;
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u32 dier = 0;
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int i, ret;
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list_for_each_entry(event_node, &counter->events_list, l) {
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switch (event_node->event) {
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@ -367,6 +461,12 @@ static int stm32_count_events_configure(struct counter_device *counter)
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regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF);
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dier |= TIM_DIER_UIE;
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break;
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case COUNTER_EVENT_CAPTURE:
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ret = stm32_count_capture_configure(counter, event_node->channel, true);
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if (ret)
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return ret;
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dier |= TIM_DIER_CC_IE(event_node->channel);
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break;
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default:
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/* should never reach this path */
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return -EINVAL;
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@ -376,6 +476,15 @@ static int stm32_count_events_configure(struct counter_device *counter)
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/* Enable / disable all events at once, from events_list, so write all DIER bits */
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regmap_write(priv->regmap, TIM_DIER, dier);
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/* check for disabled capture events */
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for (i = 0 ; i < priv->nchannels; i++) {
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if (!(dier & TIM_DIER_CC_IE(i))) {
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ret = stm32_count_capture_configure(counter, i, false);
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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@ -389,6 +498,12 @@ static int stm32_count_watch_validate(struct counter_device *counter,
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return -EOPNOTSUPP;
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switch (watch->event) {
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case COUNTER_EVENT_CAPTURE:
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if (watch->channel >= priv->nchannels) {
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dev_err(counter->parent, "Invalid channel %d\n", watch->channel);
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return -EINVAL;
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}
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return 0;
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case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
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return 0;
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default:
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@ -499,6 +614,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr)
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */
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u32 sr, dier;
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int i;
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regmap_read(priv->regmap, TIM_SR, &sr);
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regmap_read(priv->regmap, TIM_DIER, &dier);
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@ -506,7 +622,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr)
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* Some status bits in SR don't match with the enable bits in DIER. Only take care of
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* the possibly enabled bits in DIER (that matches in between SR and DIER).
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*/
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dier &= TIM_DIER_UIE;
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dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE);
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sr &= dier;
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if (sr & TIM_SR_UIF) {
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@ -519,6 +635,15 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr)
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clr &= ~TIM_SR_UIF;
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}
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/* Check capture events */
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for (i = 0 ; i < priv->nchannels; i++) {
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if (sr & TIM_SR_CC_IF(i)) {
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counter_push_event(counter, COUNTER_EVENT_CAPTURE, i);
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clr &= ~TIM_SR_CC_IF(i);
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dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i);
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}
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}
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regmap_write(priv->regmap, TIM_SR, clr);
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return IRQ_HANDLED;
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@ -633,8 +758,11 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev)
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}
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} else {
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for (i = 0; i < priv->nr_irqs; i++) {
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/* Only take care of update IRQ for overflow events */
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if (i != STM32_TIMERS_IRQ_UP)
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/*
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* Only take care of update IRQ for overflow events, and cc for
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* capture events.
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*/
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if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC)
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continue;
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ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr,
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@ -41,6 +41,11 @@
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#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
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#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
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#define TIM_DIER_UIE BIT(0) /* Update interrupt */
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#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
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#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
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#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
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#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
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#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
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#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
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#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
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#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
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@ -49,6 +54,7 @@
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#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
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#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
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#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
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#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
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#define TIM_EGR_UG BIT(0) /* Update Generation */
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#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
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#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
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@ -60,16 +66,23 @@
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#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
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#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
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#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
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#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
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#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
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#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
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#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
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#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
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#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
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#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
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#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
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#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
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#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
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#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
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#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
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#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
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#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
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#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
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#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
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#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
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#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
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#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
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#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
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