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cxgb4: Query firmware for T5 ULPTX MEMWRITE DSGL capabilities

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Query firmware to see whether we're allowed to use T5 ULPTX MEMWRITE DSGL
capabilities.  Also pass that information to Upper Layer Drivers via the
new (struct cxgb4_lld_info).ulptx_memwrite_dsgl boolean.

Based on original work by Casey Leedom <leedom@chelsio.com>

Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Kumar Sanghvi 2014-02-18 17:56:12 +05:30 committed by David S. Miller
parent 4fe44dd776
commit 1ac0f09563
4 changed files with 19 additions and 0 deletions
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1
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
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@ -308,6 +308,7 @@ struct adapter_params {
unsigned char bypass; unsigned char bypass;
unsigned int ofldq_wr_cred; unsigned int ofldq_wr_cred;
bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
}; };
#include "t4fw_api.h" #include "t4fw_api.h"

16
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
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@ -3776,6 +3776,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
lli.dbfifo_int_thresh = dbfifo_int_thresh; lli.dbfifo_int_thresh = dbfifo_int_thresh;
lli.sge_pktshift = adap->sge.pktshift; lli.sge_pktshift = adap->sge.pktshift;
lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN; lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
handle = ulds[uld].add(&lli); handle = ulds[uld].add(&lli);
if (IS_ERR(handle)) { if (IS_ERR(handle)) {
@ -5380,6 +5381,21 @@ static int adap_init0(struct adapter *adap)
val[0] = 1; val[0] = 1;
(void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val); (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
/*
* Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
* capability. Earlier versions of the firmware didn't have the
* ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
* permission to use ULPTX MEMWRITE DSGL.
*/
if (is_t4(adap->params.chip)) {
adap->params.ulptx_memwrite_dsgl = false;
} else {
params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
1, params, val);
adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
}
/* /*
* Get device capabilities so we can determine what resources we need * Get device capabilities so we can determine what resources we need
* to manage. * to manage.

1
drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
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@ -253,6 +253,7 @@ struct cxgb4_lld_info {
/* packet data */ /* packet data */
bool enable_fw_ofld_conn; /* Enable connection through fw */ bool enable_fw_ofld_conn; /* Enable connection through fw */
/* WR */ /* WR */
bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
}; };
struct cxgb4_uld_info { struct cxgb4_uld_info {

1
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View File

@ -932,6 +932,7 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_FWREV = 0x0B, FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
FW_PARAMS_PARAM_DEV_TPREV = 0x0C, FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
FW_PARAMS_PARAM_DEV_CF = 0x0D, FW_PARAMS_PARAM_DEV_CF = 0x0D,
FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
}; };
/* /*