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Char/Misc driver fixes for 6.0-rc7

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Here are 3 tiny driver fixes for 6.0-rc7.  They include:
 	- phy driver reset bugfix
 	- fpga memleak bugfix
 	- counter irq config bugfix
 
 The first 2 have been in linux-next for a while, the last one has only
 been added to my tree in the past few days, but was in linux-next under
 a different commit id.  I couldn't pull directly from the counter tree
 due to some gpg key propagation issue, so I took the commit directly
 from email instead.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg KH:
 "Here are three tiny driver fixes for 6.0-rc7.  They include:

   - phy driver reset bugfix

   - fpga memleak bugfix

   - counter irq config bugfix

  The first two have been in linux-next for a while, the last one has
  only been added to my tree in the past few days, but was in linux-next
  under a different commit id. I couldn't pull directly from the counter
  tree due to some gpg key propagation issue, so I took the commit
  directly from email instead"

* tag 'char-misc-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  counter: 104-quad-8: Fix skipped IRQ lines during events configuration
  fpga: m10bmc-sec: Fix possible memory leak of flash_buf
  phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support
This commit is contained in:
Linus Torvalds 2022-09-24 08:46:07 -07:00
commit 1a61b82856
3 changed files with 24 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/counter/104-quad-8.c
View File

@ -449,6 +449,9 @@ static int quad8_events_configure(struct counter_device *counter)
return -EINVAL;
}
/* Enable IRQ line */
irq_enabled |= BIT(event_node->channel);
/* Skip configuration if it is the same as previously set */
if (priv->irq_trigger[event_node->channel] == next_irq_trigger)
continue;
@ -462,9 +465,6 @@ static int quad8_events_configure(struct counter_device *counter)
priv->irq_trigger[event_node->channel] << 3;
iowrite8(QUAD8_CTR_IOR | ior_cfg,
&priv->reg->channel[event_node->channel].control);
/* Enable IRQ line */
irq_enabled |= BIT(event_node->channel);
}
iowrite8(irq_enabled, &priv->reg->index_interrupt);

8
drivers/fpga/intel-m10-bmc-sec-update.c
View File

@ -148,10 +148,6 @@ static ssize_t flash_count_show(struct device *dev,
stride = regmap_get_reg_stride(sec->m10bmc->regmap);
num_bits = FLASH_COUNT_SIZE * 8;
flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
if (!flash_buf)
return -ENOMEM;
if (FLASH_COUNT_SIZE % stride) {
dev_err(sec->dev,
"FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n",
@ -160,6 +156,10 @@ static ssize_t flash_count_show(struct device *dev,
return -EINVAL;
}
flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
if (!flash_buf)
return -ENOMEM;
ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
flash_buf, FLASH_COUNT_SIZE / stride);
if (ret) {

87
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
View File

@ -274,7 +274,6 @@ struct mvebu_a3700_comphy_lane {
int submode;
bool invert_tx;
bool invert_rx;
bool needs_reset;
};
struct gbe_phy_init_data_fix {
@ -1097,40 +1096,12 @@ mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)
0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
}
static int mvebu_a3700_comphy_reset(struct phy *phy)
static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)
{
struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
u16 mask, data;
dev_dbg(lane->dev, "resetting lane %d\n", lane->id);
/* COMPHY reset for internal logic */
comphy_lane_reg_set(lane, COMPHY_SFT_RESET,
SFT_RST_NO_REG, SFT_RST_NO_REG);
/* COMPHY register reset (cleared automatically) */
comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
/* PIPE soft and register reset */
data = PIPE_SOFT_RESET | PIPE_REG_RESET;
mask = data;
comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
/* Release PIPE register reset */
comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL,
0x0, PIPE_REG_RESET);
/* Reset SB configuration register (only for lanes 0 and 1) */
if (lane->id == 0 || lane->id == 1) {
u32 mask, data;
data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT |
PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT;
comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
}
return 0;
/*
* The USB3 MAC sets the USB3 PHY to low state, so we do not
* need to power off USB3 PHY again.
*/
}
static bool mvebu_a3700_comphy_check_mode(int lane,
@ -1171,10 +1142,6 @@ static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
(lane->mode != mode || lane->submode != submode))
return -EBUSY;
/* If changing mode, ensure reset is called */
if (lane->mode != PHY_MODE_INVALID && lane->mode != mode)
lane->needs_reset = true;
/* Just remember the mode, ->power_on() will do the real setup */
lane->mode = mode;
lane->submode = submode;
@ -1185,7 +1152,6 @@ static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
static int mvebu_a3700_comphy_power_on(struct phy *phy)
{
struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
int ret;
if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,
lane->submode)) {
@ -1193,14 +1159,6 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy)
return -EINVAL;
}
if (lane->needs_reset) {
ret = mvebu_a3700_comphy_reset(phy);
if (ret)
return ret;
lane->needs_reset = false;
}
switch (lane->mode) {
case PHY_MODE_USB_HOST_SS:
dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
@ -1224,38 +1182,28 @@ static int mvebu_a3700_comphy_power_off(struct phy *phy)
{
struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
switch (lane->mode) {
case PHY_MODE_USB_HOST_SS:
/*
* The USB3 MAC sets the USB3 PHY to low state, so we do not
* need to power off USB3 PHY again.
*/
break;
case PHY_MODE_SATA:
mvebu_a3700_comphy_sata_power_off(lane);
break;
case PHY_MODE_ETHERNET:
switch (lane->id) {
case 0:
mvebu_a3700_comphy_usb3_power_off(lane);
mvebu_a3700_comphy_ethernet_power_off(lane);
break;
case PHY_MODE_PCIE:
return 0;
case 1:
mvebu_a3700_comphy_pcie_power_off(lane);
break;
mvebu_a3700_comphy_ethernet_power_off(lane);
return 0;
case 2:
mvebu_a3700_comphy_usb3_power_off(lane);
mvebu_a3700_comphy_sata_power_off(lane);
return 0;
default:
dev_err(lane->dev, "invalid COMPHY mode\n");
return -EINVAL;
}
return 0;
}
static const struct phy_ops mvebu_a3700_comphy_ops = {
.power_on = mvebu_a3700_comphy_power_on,
.power_off = mvebu_a3700_comphy_power_off,
.reset = mvebu_a3700_comphy_reset,
.set_mode = mvebu_a3700_comphy_set_mode,
.owner = THIS_MODULE,
};
@ -1393,8 +1341,7 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
* To avoid relying on the bootloader/firmware configuration,
* power off all comphys.
*/
mvebu_a3700_comphy_reset(phy);
lane->needs_reset = false;
mvebu_a3700_comphy_power_off(phy);
}
provider = devm_of_phy_provider_register(&pdev->dev,