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drm/amdgpu: Add Fiji support to the SDMA 3.0 IP module

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Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
David Zhang 2015-07-08 17:29:27 +08:00 committed by Alex Deucher
parent af15a2d51d
commit 1a5bbb6695
2 changed files with 38 additions and 0 deletions
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31
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
View File

@ -53,6 +53,8 @@ MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
{ {
@ -80,6 +82,24 @@ static const u32 tonga_mgcg_cgcg_init[] =
mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
}; };
static const u32 golden_settings_fiji_a10[] =
{
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
};
static const u32 fiji_mgcg_cgcg_init[] =
{
mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
};
static const u32 cz_golden_settings_a11[] = static const u32 cz_golden_settings_a11[] =
{ {
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
@ -122,6 +142,14 @@ static const u32 cz_mgcg_cgcg_init[] =
static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_fiji_a10,
(const u32)ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
@ -167,6 +195,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
case CHIP_TONGA: case CHIP_TONGA:
chip_name = "tonga"; chip_name = "tonga";
break; break;
case CHIP_FIJI:
chip_name = "fiji";
break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
chip_name = "carrizo"; chip_name = "carrizo";
break; break;

7
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -1209,6 +1209,13 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
.rev = 0, .rev = 0,
.funcs = &gfx_v8_0_ip_funcs, .funcs = &gfx_v8_0_ip_funcs,
}, },
{
.type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 3,
.minor = 0,
.rev = 0,
.funcs = &sdma_v3_0_ip_funcs,
},
}; };
static const struct amdgpu_ip_block_version cz_ip_blocks[] = static const struct amdgpu_ip_block_version cz_ip_blocks[] =