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Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 UV3 support update from Ingo Molnar: "Support for the SGI Ultraviolet System 3 (UV3) platform - the upcoming third major iteration and upscaling of the SGI UV supercomputing platform." * 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, uv, uv3: Trim MMR register definitions after code changes for SGI UV3 x86, uv, uv3: Check current gru hub support for SGI UV3 x86, uv, uv3: Update Time Support for SGI UV3 x86, uv, uv3: Update x2apic Support for SGI UV3 x86, uv, uv3: Update Hub Info for SGI UV3 x86, uv, uv3: Update ACPI Check to include SGI UV3 x86, uv, uv3: Update MMR register definitions for SGI Ultraviolet System 3 (UV3)
This commit is contained in:
Linus Torvalds
commit
1a13c0b181
@ -5,7 +5,7 @@
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*
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* SGI UV architectural definitions
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*
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* Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_HUB_H
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@ -175,6 +175,7 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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*/
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#define UV1_HUB_REVISION_BASE 1
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#define UV2_HUB_REVISION_BASE 3
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#define UV3_HUB_REVISION_BASE 5
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static inline int is_uv1_hub(void)
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{
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@ -182,6 +183,23 @@ static inline int is_uv1_hub(void)
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}
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static inline int is_uv2_hub(void)
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{
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return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
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(uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
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}
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static inline int is_uv3_hub(void)
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{
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return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE;
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}
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static inline int is_uv_hub(void)
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{
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return uv_hub_info->hub_revision;
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}
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/* code common to uv2 and uv3 only */
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static inline int is_uvx_hub(void)
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{
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return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
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}
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@ -230,14 +248,23 @@ union uvh_apicid {
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#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
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#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
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#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE \
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: UV2_LOCAL_MMR_BASE)
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#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE \
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: UV2_GLOBAL_MMR32_BASE)
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#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
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UV2_LOCAL_MMR_SIZE)
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#define UV3_LOCAL_MMR_BASE 0xfa000000UL
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#define UV3_GLOBAL_MMR32_BASE 0xfc000000UL
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#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
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#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
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#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
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(is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
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UV3_LOCAL_MMR_BASE))
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#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\
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(is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\
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UV3_GLOBAL_MMR32_BASE))
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#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
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(is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
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UV3_LOCAL_MMR_SIZE))
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#define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
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UV2_GLOBAL_MMR32_SIZE)
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(is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\
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UV3_GLOBAL_MMR32_SIZE))
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#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
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#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
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@ -599,6 +626,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
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* 1 - UV1 rev 1.0 initial silicon
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* 2 - UV1 rev 2.0 production silicon
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* 3 - UV2 rev 1.0 initial silicon
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* 5 - UV3 rev 1.0 initial silicon
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*/
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static inline int uv_get_min_hub_revision_id(void)
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{
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File diff suppressed because it is too large
Load Diff
@ -5,7 +5,7 @@
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*
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* SGI UV APIC functions (note: not an Intel compatible APIC)
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*
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* Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/cpumask.h>
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#include <linux/hardirq.h>
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@ -91,10 +91,16 @@ static int __init early_get_pnodeid(void)
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m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
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uv_min_hub_revision_id = node_id.s.revision;
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if (node_id.s.part_number == UV2_HUB_PART_NUMBER)
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uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
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if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X)
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switch (node_id.s.part_number) {
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case UV2_HUB_PART_NUMBER:
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case UV2_HUB_PART_NUMBER_X:
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uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
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break;
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case UV3_HUB_PART_NUMBER:
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case UV3_HUB_PART_NUMBER_X:
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uv_min_hub_revision_id += UV3_HUB_REVISION_BASE - 1;
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break;
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}
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uv_hub_info->hub_revision = uv_min_hub_revision_id;
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pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
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@ -130,13 +136,16 @@ static void __init uv_set_apicid_hibit(void)
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static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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int pnodeid, is_uv1, is_uv2;
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int pnodeid, is_uv1, is_uv2, is_uv3;
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is_uv1 = !strcmp(oem_id, "SGI");
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is_uv2 = !strcmp(oem_id, "SGI2");
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if (is_uv1 || is_uv2) {
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is_uv3 = !strncmp(oem_id, "SGI3", 4); /* there are varieties of UV3 */
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if (is_uv1 || is_uv2 || is_uv3) {
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uv_hub_info->hub_revision =
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is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE;
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(is_uv1 ? UV1_HUB_REVISION_BASE :
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(is_uv2 ? UV2_HUB_REVISION_BASE :
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UV3_HUB_REVISION_BASE));
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pnodeid = early_get_pnodeid();
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early_get_apic_pnode_shift();
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x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
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@ -450,14 +459,17 @@ static __init void map_high(char *id, unsigned long base, int pshift,
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paddr = base << pshift;
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bytes = (1UL << bshift) * (max_pnode + 1);
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printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
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paddr + bytes);
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if (!paddr) {
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pr_info("UV: Map %s_HI base address NULL\n", id);
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return;
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}
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pr_info("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
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if (map_type == map_uc)
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init_extra_mapping_uc(paddr, bytes);
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else
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init_extra_mapping_wb(paddr, bytes);
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}
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static __init void map_gru_high(int max_pnode)
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{
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union uvh_rh_gam_gru_overlay_config_mmr_u gru;
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@ -468,7 +480,8 @@ static __init void map_gru_high(int max_pnode)
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map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
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gru_start_paddr = ((u64)gru.s.base << shift);
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gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
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} else {
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pr_info("UV: GRU disabled\n");
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}
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}
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@ -480,23 +493,146 @@ static __init void map_mmr_high(int max_pnode)
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mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
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if (mmr.s.enable)
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map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
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else
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pr_info("UV: MMR disabled\n");
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}
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static __init void map_mmioh_high(int max_pnode)
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/*
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* This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
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* and REDIRECT MMR regs are exactly the same on UV3.
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*/
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struct mmioh_config {
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unsigned long overlay;
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unsigned long redirect;
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char *id;
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};
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static __initdata struct mmioh_config mmiohs[] = {
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{
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UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
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UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
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"MMIOH0"
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},
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{
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UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
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UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
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"MMIOH1"
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},
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};
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static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
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{
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union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
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unsigned long mmr;
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unsigned long base;
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int i, n, shift, m_io, max_io;
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int nasid, lnasid, fi, li;
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char *id;
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id = mmiohs[index].id;
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overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
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pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
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id, overlay.v, overlay.s3.base, overlay.s3.m_io);
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if (!overlay.s3.enable) {
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pr_info("UV: %s disabled\n", id);
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return;
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}
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shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
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base = (unsigned long)overlay.s3.base;
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m_io = overlay.s3.m_io;
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mmr = mmiohs[index].redirect;
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n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
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min_pnode *= 2; /* convert to NASID */
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max_pnode *= 2;
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max_io = lnasid = fi = li = -1;
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for (i = 0; i < n; i++) {
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union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
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redirect.v = uv_read_local_mmr(mmr + i * 8);
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nasid = redirect.s3.nasid;
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if (nasid < min_pnode || max_pnode < nasid)
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nasid = -1; /* invalid NASID */
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if (nasid == lnasid) {
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li = i;
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if (i != n-1) /* last entry check */
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continue;
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}
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/* check if we have a cached (or last) redirect to print */
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if (lnasid != -1 || (i == n-1 && nasid != -1)) {
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unsigned long addr1, addr2;
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int f, l;
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if (lnasid == -1) {
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f = l = i;
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lnasid = nasid;
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} else {
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f = fi;
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l = li;
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}
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addr1 = (base << shift) +
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f * (unsigned long)(1 << m_io);
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addr2 = (base << shift) +
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(l + 1) * (unsigned long)(1 << m_io);
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pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
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id, fi, li, lnasid, addr1, addr2);
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if (max_io < l)
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max_io = l;
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}
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fi = li = i;
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lnasid = nasid;
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}
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pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
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id, base, shift, m_io, max_io);
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if (max_io >= 0)
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map_high(id, base, shift, m_io, max_io, map_uc);
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}
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static __init void map_mmioh_high(int min_pnode, int max_pnode)
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{
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union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
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int shift;
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unsigned long mmr, base;
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int shift, enable, m_io, n_io;
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mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
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if (is_uv1_hub() && mmioh.s1.enable) {
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shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
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map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io,
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max_pnode, map_uc);
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if (is_uv3_hub()) {
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/* Map both MMIOH Regions */
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map_mmioh_high_uv3(0, min_pnode, max_pnode);
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map_mmioh_high_uv3(1, min_pnode, max_pnode);
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return;
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}
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if (is_uv2_hub() && mmioh.s2.enable) {
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if (is_uv1_hub()) {
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mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
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shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
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mmioh.v = uv_read_local_mmr(mmr);
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enable = !!mmioh.s1.enable;
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base = mmioh.s1.base;
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m_io = mmioh.s1.m_io;
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n_io = mmioh.s1.n_io;
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} else if (is_uv2_hub()) {
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mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
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shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
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map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io,
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max_pnode, map_uc);
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mmioh.v = uv_read_local_mmr(mmr);
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enable = !!mmioh.s2.enable;
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base = mmioh.s2.base;
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m_io = mmioh.s2.m_io;
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n_io = mmioh.s2.n_io;
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} else
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return;
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if (enable) {
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max_pnode &= (1 << n_io) - 1;
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pr_info(
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"UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
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base, shift, m_io, n_io, max_pnode);
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map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
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} else {
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pr_info("UV: MMIOH disabled\n");
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}
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}
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@ -724,42 +860,41 @@ void uv_nmi_init(void)
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void __init uv_system_init(void)
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{
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union uvh_rh_gam_config_mmr_u m_n_config;
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union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
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union uvh_node_id_u node_id;
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unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
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int gnode_extra, max_pnode = 0;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
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int gnode_extra, min_pnode = 999999, max_pnode = -1;
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unsigned long mmr_base, present, paddr;
|
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unsigned short pnode_mask, pnode_io_mask;
|
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unsigned short pnode_mask;
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char *hub = (is_uv1_hub() ? "UV1" :
|
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(is_uv2_hub() ? "UV2" :
|
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"UV3"));
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printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2");
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pr_info("UV: Found %s hub\n", hub);
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map_low_mmrs();
|
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|
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m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
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m_val = m_n_config.s.m_skt;
|
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n_val = m_n_config.s.n_skt;
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mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
|
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n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io;
|
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pnode_mask = (1 << n_val) - 1;
|
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mmr_base =
|
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uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
|
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~UV_MMR_ENABLE;
|
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pnode_mask = (1 << n_val) - 1;
|
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pnode_io_mask = (1 << n_io) - 1;
|
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|
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node_id.v = uv_read_local_mmr(UVH_NODE_ID);
|
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gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
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gnode_upper = ((unsigned long)gnode_extra << m_val);
|
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printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
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n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
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pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x\n",
|
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n_val, m_val, pnode_mask, gnode_upper, gnode_extra);
|
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|
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printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
|
||||
pr_info("UV: global MMR base 0x%lx\n", mmr_base);
|
||||
|
||||
for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
|
||||
uv_possible_blades +=
|
||||
hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
|
||||
|
||||
/* uv_num_possible_blades() is really the hub count */
|
||||
printk(KERN_INFO "UV: Found %d blades, %d hubs\n",
|
||||
pr_info("UV: Found %d blades, %d hubs\n",
|
||||
is_uv1_hub() ? uv_num_possible_blades() :
|
||||
(uv_num_possible_blades() + 1) / 2,
|
||||
uv_num_possible_blades());
|
||||
@ -794,6 +929,7 @@ void __init uv_system_init(void)
|
||||
uv_blade_info[blade].nr_possible_cpus = 0;
|
||||
uv_blade_info[blade].nr_online_cpus = 0;
|
||||
spin_lock_init(&uv_blade_info[blade].nmi_lock);
|
||||
min_pnode = min(pnode, min_pnode);
|
||||
max_pnode = max(pnode, max_pnode);
|
||||
blade++;
|
||||
}
|
||||
@ -856,7 +992,7 @@ void __init uv_system_init(void)
|
||||
|
||||
map_gru_high(max_pnode);
|
||||
map_mmr_high(max_pnode);
|
||||
map_mmioh_high(max_pnode & pnode_io_mask);
|
||||
map_mmioh_high(min_pnode, max_pnode);
|
||||
|
||||
uv_cpu_init();
|
||||
uv_scir_register_cpu_notifier();
|
||||
|
||||
@ -548,8 +548,7 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
|
||||
if (cfg->address < 0xFFFFFFFF)
|
||||
return 0;
|
||||
|
||||
if (!strcmp(mcfg->header.oem_id, "SGI") ||
|
||||
!strcmp(mcfg->header.oem_id, "SGI2"))
|
||||
if (!strncmp(mcfg->header.oem_id, "SGI", 3))
|
||||
return 0;
|
||||
|
||||
if (mcfg->header.revision >= 1) {
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
|
||||
* Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved.
|
||||
* Copyright (c) Dimitri Sivanich
|
||||
*/
|
||||
#include <linux/clockchips.h>
|
||||
@ -102,9 +102,10 @@ static int uv_intr_pending(int pnode)
|
||||
if (is_uv1_hub())
|
||||
return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
|
||||
UV1H_EVENT_OCCURRED0_RTC1_MASK;
|
||||
else
|
||||
return uv_read_global_mmr64(pnode, UV2H_EVENT_OCCURRED2) &
|
||||
UV2H_EVENT_OCCURRED2_RTC_1_MASK;
|
||||
else if (is_uvx_hub())
|
||||
return uv_read_global_mmr64(pnode, UVXH_EVENT_OCCURRED2) &
|
||||
UVXH_EVENT_OCCURRED2_RTC_1_MASK;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Setup interrupt and return non-zero if early expiration occurred. */
|
||||
@ -122,8 +123,8 @@ static int uv_setup_intr(int cpu, u64 expires)
|
||||
uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
|
||||
UV1H_EVENT_OCCURRED0_RTC1_MASK);
|
||||
else
|
||||
uv_write_global_mmr64(pnode, UV2H_EVENT_OCCURRED2_ALIAS,
|
||||
UV2H_EVENT_OCCURRED2_RTC_1_MASK);
|
||||
uv_write_global_mmr64(pnode, UVXH_EVENT_OCCURRED2_ALIAS,
|
||||
UVXH_EVENT_OCCURRED2_RTC_1_MASK);
|
||||
|
||||
val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
|
||||
((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
|
||||
|
||||
@ -517,7 +517,7 @@ static int __init gru_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!is_uv_system())
|
||||
if (!is_uv_system() || (is_uvx_hub() && !is_uv2_hub()))
|
||||
return 0;
|
||||
|
||||
#if defined CONFIG_IA64
|
||||
|
||||
Loading…
Reference in New Issue
Block a user