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MIPS: ralink: adds irq code
All of the Ralink Wifi SoC currently supported by this series share the same interrupt controller (INTC). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4890/
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John Crispin
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8563991026
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176
arch/mips/ralink/irq.c
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176
arch/mips/ralink/irq.c
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include "common.h"
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/* INTC register offsets */
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#define INTC_REG_STATUS0 0x00
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#define INTC_REG_STATUS1 0x04
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#define INTC_REG_TYPE 0x20
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#define INTC_REG_RAW_STATUS 0x30
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#define INTC_REG_ENABLE 0x34
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#define INTC_REG_DISABLE 0x38
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#define INTC_INT_GLOBAL BIT(31)
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#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
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#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
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#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
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#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
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/* we have a cascade of 8 irqs */
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#define RALINK_INTC_IRQ_BASE 8
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/* we have 32 SoC irqs */
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#define RALINK_INTC_IRQ_COUNT 32
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#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
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static void __iomem *rt_intc_membase;
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static inline void rt_intc_w32(u32 val, unsigned reg)
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{
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__raw_writel(val, rt_intc_membase + reg);
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}
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static inline u32 rt_intc_r32(unsigned reg)
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{
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return __raw_readl(rt_intc_membase + reg);
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}
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static void ralink_intc_irq_unmask(struct irq_data *d)
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{
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rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
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}
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static void ralink_intc_irq_mask(struct irq_data *d)
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{
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rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
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}
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static struct irq_chip ralink_intc_irq_chip = {
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.name = "INTC",
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.irq_unmask = ralink_intc_irq_unmask,
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.irq_mask = ralink_intc_irq_mask,
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.irq_mask_ack = ralink_intc_irq_mask,
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};
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unsigned int __cpuinit get_c0_compare_int(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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u32 pending = rt_intc_r32(INTC_REG_STATUS0);
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if (pending) {
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struct irq_domain *domain = irq_get_handler_data(irq);
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generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
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} else {
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spurious_interrupt();
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(RALINK_CPU_IRQ_COUNTER);
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else if (pending & STATUSF_IP5)
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do_IRQ(RALINK_CPU_IRQ_FE);
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else if (pending & STATUSF_IP6)
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do_IRQ(RALINK_CPU_IRQ_WIFI);
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else if (pending & STATUSF_IP2)
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do_IRQ(RALINK_CPU_IRQ_INTC);
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else
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spurious_interrupt();
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}
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static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = intc_map,
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};
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static int __init intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct resource res;
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struct irq_domain *domain;
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mips_cpu_irq_init();
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if (of_address_to_resource(node, 0, &res))
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panic("Failed to get intc memory range");
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if (request_mem_region(res.start, resource_size(&res),
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res.name) < 0)
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pr_err("Failed to request intc memory");
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rt_intc_membase = ioremap_nocache(res.start,
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resource_size(&res));
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if (!rt_intc_membase)
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panic("Failed to remap intc memory");
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/* disable all interrupts */
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rt_intc_w32(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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rt_intc_w32(0, INTC_REG_TYPE);
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domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
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RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add irqdomain");
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rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
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irq_set_chained_handler(RALINK_CPU_IRQ_INTC, ralink_intc_irq_handler);
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irq_set_handler_data(RALINK_CPU_IRQ_INTC, domain);
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cp0_perfcount_irq = irq_create_mapping(domain, 9);
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return 0;
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}
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static struct of_device_id __initdata of_irq_ids[] = {
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{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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of_irq_init(of_irq_ids);
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}
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