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ARM: omap1: dma: remove omap2 specific bits
No part of plat-omap/dma.c is called on omap2 any more, so anything omap2 specific in here can simply be removed. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
52ef8efcb7
commit
19491c2215
@ -34,11 +34,9 @@
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#include <linux/omap-dma.h>
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#ifdef CONFIG_ARCH_OMAP1
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#include <mach/hardware.h>
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#include <linux/soc/ti/omap1-io.h>
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#include <linux/soc/ti/omap1-soc.h>
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#endif
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/*
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* MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
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@ -51,16 +49,7 @@
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#undef DEBUG
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#ifndef CONFIG_ARCH_OMAP1
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enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
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DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
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};
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enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
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#endif
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#define OMAP_DMA_ACTIVE 0x01
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#define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
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#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
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@ -94,13 +83,9 @@ static inline void omap_disable_channel_irq(int lch)
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/* disable channel interrupts */
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p->dma_write(0, CICR, lch);
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/* Clear CSR */
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if (dma_omap1())
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p->dma_read(CSR, lch);
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else
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p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
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p->dma_read(CSR, lch);
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}
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#ifdef CONFIG_ARCH_OMAP1
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static inline void set_gdma_dev(int req, int dev)
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{
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u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
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@ -112,11 +97,6 @@ static inline void set_gdma_dev(int req, int dev)
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l |= (dev - 1) << shift;
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omap_writel(l, reg);
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}
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#else
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#define set_gdma_dev(req, dev) do {} while (0)
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#define omap_readl(reg) 0
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#define omap_writel(val, reg) do {} while (0)
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#endif
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#ifdef CONFIG_ARCH_OMAP1
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void omap_set_dma_priority(int lch, int dst_port, int priority)
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@ -181,59 +161,24 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
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int dma_trigger, int src_or_dst_synch)
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{
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u32 l;
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u16 ccr;
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l = p->dma_read(CSDP, lch);
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l &= ~0x03;
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l |= data_type;
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p->dma_write(l, CSDP, lch);
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if (dma_omap1()) {
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u16 ccr;
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ccr = p->dma_read(CCR, lch);
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ccr &= ~(1 << 5);
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if (sync_mode == OMAP_DMA_SYNC_FRAME)
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ccr |= 1 << 5;
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p->dma_write(ccr, CCR, lch);
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ccr = p->dma_read(CCR2, lch);
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ccr &= ~(1 << 2);
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if (sync_mode == OMAP_DMA_SYNC_BLOCK)
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ccr |= 1 << 2;
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p->dma_write(ccr, CCR2, lch);
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}
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if (dma_omap2plus() && dma_trigger) {
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u32 val;
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val = p->dma_read(CCR, lch);
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/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
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val &= ~((1 << 23) | (3 << 19) | 0x1f);
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val |= (dma_trigger & ~0x1f) << 14;
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val |= dma_trigger & 0x1f;
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if (sync_mode & OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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else
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val &= ~(1 << 5);
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if (sync_mode & OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 18;
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else
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val &= ~(1 << 18);
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if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
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val &= ~(1 << 24); /* dest synch */
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val |= (1 << 23); /* Prefetch */
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} else if (src_or_dst_synch) {
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val |= 1 << 24; /* source synch */
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} else {
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val &= ~(1 << 24); /* dest synch */
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}
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p->dma_write(val, CCR, lch);
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}
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ccr = p->dma_read(CCR, lch);
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ccr &= ~(1 << 5);
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if (sync_mode == OMAP_DMA_SYNC_FRAME)
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ccr |= 1 << 5;
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p->dma_write(ccr, CCR, lch);
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ccr = p->dma_read(CCR2, lch);
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ccr &= ~(1 << 2);
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if (sync_mode == OMAP_DMA_SYNC_BLOCK)
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ccr |= 1 << 2;
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p->dma_write(ccr, CCR2, lch);
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p->dma_write(elem_count, CEN, lch);
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p->dma_write(frame_count, CFN, lch);
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}
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@ -241,7 +186,7 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
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void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
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{
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if (dma_omap1() && !dma_omap15xx()) {
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if (!dma_omap15xx()) {
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u32 l;
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l = p->dma_read(LCH_CTRL, lch);
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@ -258,15 +203,12 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
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int src_ei, int src_fi)
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{
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u32 l;
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u16 w;
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if (dma_omap1()) {
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u16 w;
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w = p->dma_read(CSDP, lch);
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w &= ~(0x1f << 2);
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w |= src_port << 2;
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p->dma_write(w, CSDP, lch);
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}
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w = p->dma_read(CSDP, lch);
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w &= ~(0x1f << 2);
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w |= src_port << 2;
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p->dma_write(w, CSDP, lch);
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l = p->dma_read(CCR, lch);
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l &= ~(0x03 << 12);
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@ -304,26 +246,15 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
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case OMAP_DMA_DATA_BURST_DIS:
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break;
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case OMAP_DMA_DATA_BURST_4:
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if (dma_omap2plus())
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burst = 0x1;
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else
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burst = 0x2;
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burst = 0x2;
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break;
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case OMAP_DMA_DATA_BURST_8:
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if (dma_omap2plus()) {
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burst = 0x2;
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break;
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}
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/*
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* not supported by current hardware on OMAP1
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* w |= (0x03 << 7);
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*/
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fallthrough;
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case OMAP_DMA_DATA_BURST_16:
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if (dma_omap2plus()) {
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burst = 0x3;
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break;
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}
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/* OMAP1 don't support burst 16 */
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fallthrough;
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default:
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@ -342,12 +273,10 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
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{
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u32 l;
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if (dma_omap1()) {
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l = p->dma_read(CSDP, lch);
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l &= ~(0x1f << 9);
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l |= dest_port << 9;
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p->dma_write(l, CSDP, lch);
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}
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l = p->dma_read(CSDP, lch);
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l &= ~(0x1f << 9);
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l |= dest_port << 9;
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p->dma_write(l, CSDP, lch);
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l = p->dma_read(CCR, lch);
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l &= ~(0x03 << 14);
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@ -385,22 +314,12 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
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case OMAP_DMA_DATA_BURST_DIS:
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break;
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case OMAP_DMA_DATA_BURST_4:
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if (dma_omap2plus())
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burst = 0x1;
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else
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burst = 0x2;
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burst = 0x2;
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break;
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case OMAP_DMA_DATA_BURST_8:
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if (dma_omap2plus())
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burst = 0x2;
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else
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burst = 0x3;
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burst = 0x3;
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break;
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case OMAP_DMA_DATA_BURST_16:
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if (dma_omap2plus()) {
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burst = 0x3;
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break;
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}
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/* OMAP1 don't support burst 16 */
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fallthrough;
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default:
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@ -416,10 +335,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
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static inline void omap_enable_channel_irq(int lch)
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{
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/* Clear CSR */
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if (dma_omap1())
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p->dma_read(CSR, lch);
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else
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p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
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p->dma_read(CSR, lch);
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/* Enable some nice interrupts. */
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p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
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@ -437,8 +353,7 @@ static inline void enable_lnk(int lch)
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l = p->dma_read(CLNK_CTRL, lch);
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if (dma_omap1())
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l &= ~(1 << 14);
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l &= ~(1 << 14);
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/* Set the ENABLE_LNK bits */
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if (dma_chan[lch].next_lch != -1)
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@ -456,15 +371,8 @@ static inline void disable_lnk(int lch)
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/* Disable interrupts */
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omap_disable_channel_irq(lch);
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if (dma_omap1()) {
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/* Set the STOP_LNK bit */
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l |= 1 << 14;
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}
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if (dma_omap2plus()) {
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/* Clear the ENABLE_LNK bit */
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l &= ~(1 << 15);
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}
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/* Set the STOP_LNK bit */
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l |= 1 << 14;
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p->dma_write(l, CLNK_CTRL, lch);
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dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
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@ -508,8 +416,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
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chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
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if (dma_omap1())
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chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
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chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
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if (dma_omap16xx()) {
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/* If the sync device is set, configure it dynamically. */
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@ -522,7 +429,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
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* id.
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*/
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p->dma_write(dev_id | (1 << 10), CCR, free_ch);
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} else if (dma_omap1()) {
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} else {
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p->dma_write(dev_id, CCR, free_ch);
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}
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@ -739,8 +646,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
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offset = p->dma_read(CSSA, lch);
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}
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if (dma_omap1())
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offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
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offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
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return offset;
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}
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@ -778,8 +684,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
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offset = p->dma_read(CDSA, lch);
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}
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if (dma_omap1())
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offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
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offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
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return offset;
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}
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@ -796,9 +701,8 @@ int omap_dma_running(void)
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{
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int lch;
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if (dma_omap1())
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if (omap_lcd_dma_running())
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return 1;
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if (omap_lcd_dma_running())
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return 1;
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for (lch = 0; lch < dma_chan_count; lch++)
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if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
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@ -809,8 +713,6 @@ int omap_dma_running(void)
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/*----------------------------------------------------------------------------*/
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#ifdef CONFIG_ARCH_OMAP1
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static int omap1_dma_handle_ch(int ch)
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{
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u32 csr;
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@ -863,10 +765,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
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return handled ? IRQ_HANDLED : IRQ_NONE;
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}
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#else
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#define omap1_dma_irq_handler NULL
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#endif
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struct omap_system_dma_plat_info *omap_get_plat_info(void)
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{
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return p;
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@ -912,29 +810,27 @@ static int omap_system_dma_probe(struct platform_device *pdev)
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if (ch >= 6 && enable_1510_mode)
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continue;
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if (dma_omap1()) {
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/*
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* request_irq() doesn't like dev_id (ie. ch) being
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* zero, so we have to kludge around this.
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*/
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sprintf(&irq_name[0], "%d", ch);
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dma_irq = platform_get_irq_byname(pdev, irq_name);
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/*
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* request_irq() doesn't like dev_id (ie. ch) being
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* zero, so we have to kludge around this.
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*/
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sprintf(&irq_name[0], "%d", ch);
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dma_irq = platform_get_irq_byname(pdev, irq_name);
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if (dma_irq < 0) {
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ret = dma_irq;
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goto exit_dma_irq_fail;
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}
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/* INT_DMA_LCD is handled in lcd_dma.c */
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if (dma_irq == INT_DMA_LCD)
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continue;
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ret = request_irq(dma_irq,
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omap1_dma_irq_handler, 0, "DMA",
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(void *) (ch + 1));
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if (ret != 0)
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goto exit_dma_irq_fail;
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if (dma_irq < 0) {
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ret = dma_irq;
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goto exit_dma_irq_fail;
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}
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/* INT_DMA_LCD is handled in lcd_dma.c */
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if (dma_irq == INT_DMA_LCD)
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continue;
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ret = request_irq(dma_irq,
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omap1_dma_irq_handler, 0, "DMA",
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(void *) (ch + 1));
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if (ret != 0)
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goto exit_dma_irq_fail;
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}
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/* reserve dma channels 0 and 1 in high security devices on 34xx */
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@ -954,9 +850,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
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{
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int dma_irq, irq_rel = 0;
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if (dma_omap2plus())
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return 0;
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for ( ; irq_rel < dma_chan_count; irq_rel++) {
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dma_irq = platform_get_irq(pdev, irq_rel);
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free_irq(dma_irq, (void *)(irq_rel + 1));
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