mirror of
https://github.com/torvalds/linux.git
synced 2024-11-08 13:11:45 +00:00
ath5k: Misc fixes/cleanups
*Handle MIB interrupts and pass low level stats to mac80211 *Add Power On Self Test function *Update to match recent dumps *Let RF2425 attach so we can further test it *Remove unused files regdom.c and regdom.h base.c Changes-licensed-under: 3-clause-BSD rest Changes-licensed-under: ISC Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
John W. Linville
parent
136bfc798f
commit
194828a292
@ -450,14 +450,6 @@ struct ath5k_rx_status {
|
|||||||
#define AR5K_RXKEYIX_INVALID ((u8) - 1)
|
#define AR5K_RXKEYIX_INVALID ((u8) - 1)
|
||||||
#define AR5K_TXKEYIX_INVALID ((u32) - 1)
|
#define AR5K_TXKEYIX_INVALID ((u32) - 1)
|
||||||
|
|
||||||
struct ath5k_mib_stats {
|
|
||||||
u32 ackrcv_bad;
|
|
||||||
u32 rts_bad;
|
|
||||||
u32 rts_good;
|
|
||||||
u32 fcs_bad;
|
|
||||||
u32 beacons;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/**************************\
|
/**************************\
|
||||||
BEACON TIMERS DEFINITIONS
|
BEACON TIMERS DEFINITIONS
|
||||||
@ -1070,6 +1062,7 @@ extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
|
|||||||
extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
|
extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
|
||||||
extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
|
extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
|
||||||
extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask);
|
extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask);
|
||||||
|
extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
|
||||||
/* EEPROM access functions */
|
/* EEPROM access functions */
|
||||||
extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
|
extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
|
||||||
/* Protocol Control Unit Functions */
|
/* Protocol Control Unit Functions */
|
||||||
@ -1098,7 +1091,6 @@ extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_be
|
|||||||
extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
|
extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
|
||||||
extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
|
extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
|
||||||
#endif
|
#endif
|
||||||
extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ath5k_mib_stats *statistics);
|
|
||||||
/* ACK bit rate */
|
/* ACK bit rate */
|
||||||
void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
|
void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
|
||||||
/* ACK/CTS Timeouts */
|
/* ACK/CTS Timeouts */
|
||||||
|
|||||||
@ -2342,7 +2342,8 @@ ath5k_init(struct ath5k_softc *sc)
|
|||||||
* Enable interrupts.
|
* Enable interrupts.
|
||||||
*/
|
*/
|
||||||
sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
|
sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
|
||||||
AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
|
AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
|
||||||
|
AR5K_INT_MIB;
|
||||||
|
|
||||||
ath5k_hw_set_intr(sc->ah, sc->imask);
|
ath5k_hw_set_intr(sc->ah, sc->imask);
|
||||||
/* Set ack to be sent at low bit-rates */
|
/* Set ack to be sent at low bit-rates */
|
||||||
@ -2522,7 +2523,11 @@ ath5k_intr(int irq, void *dev_id)
|
|||||||
if (status & AR5K_INT_BMISS) {
|
if (status & AR5K_INT_BMISS) {
|
||||||
}
|
}
|
||||||
if (status & AR5K_INT_MIB) {
|
if (status & AR5K_INT_MIB) {
|
||||||
/* TODO */
|
/*
|
||||||
|
* These stats are also used for ANI i think
|
||||||
|
* so how about updating them more often ?
|
||||||
|
*/
|
||||||
|
ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
|
} while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
|
||||||
@ -3015,6 +3020,10 @@ ath5k_get_stats(struct ieee80211_hw *hw,
|
|||||||
struct ieee80211_low_level_stats *stats)
|
struct ieee80211_low_level_stats *stats)
|
||||||
{
|
{
|
||||||
struct ath5k_softc *sc = hw->priv;
|
struct ath5k_softc *sc = hw->priv;
|
||||||
|
struct ath5k_hw *ah = sc->ah;
|
||||||
|
|
||||||
|
/* Force update */
|
||||||
|
ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
|
||||||
|
|
||||||
memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
|
memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
|
||||||
|
|
||||||
|
|||||||
@ -119,12 +119,70 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
|
|||||||
Attach/Detach Functions
|
Attach/Detach Functions
|
||||||
\***************************************/
|
\***************************************/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Power On Self Test helper function
|
||||||
|
*/
|
||||||
|
static int ath5k_hw_post(struct ath5k_hw *ah)
|
||||||
|
{
|
||||||
|
|
||||||
|
int i, c;
|
||||||
|
u16 cur_reg;
|
||||||
|
u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
|
||||||
|
u32 var_pattern;
|
||||||
|
u32 static_pattern[4] = {
|
||||||
|
0x55555555, 0xaaaaaaaa,
|
||||||
|
0x66666666, 0x99999999
|
||||||
|
};
|
||||||
|
u32 init_val;
|
||||||
|
u32 cur_val;
|
||||||
|
|
||||||
|
for (c = 0; c < 2; c++) {
|
||||||
|
|
||||||
|
cur_reg = regs[c];
|
||||||
|
init_val = ath5k_hw_reg_read(ah, cur_reg);
|
||||||
|
|
||||||
|
for (i = 0; i < 256; i++) {
|
||||||
|
var_pattern = i << 16 | i;
|
||||||
|
ath5k_hw_reg_write(ah, var_pattern, cur_reg);
|
||||||
|
cur_val = ath5k_hw_reg_read(ah, cur_reg);
|
||||||
|
|
||||||
|
if (cur_val != var_pattern) {
|
||||||
|
ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
|
||||||
|
return -EAGAIN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Found on ndiswrapper dumps */
|
||||||
|
var_pattern = 0x0039080f;
|
||||||
|
ath5k_hw_reg_write(ah, var_pattern, cur_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < 4; i++) {
|
||||||
|
var_pattern = static_pattern[i];
|
||||||
|
ath5k_hw_reg_write(ah, var_pattern, cur_reg);
|
||||||
|
cur_val = ath5k_hw_reg_read(ah, cur_reg);
|
||||||
|
|
||||||
|
if (cur_val != var_pattern) {
|
||||||
|
ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
|
||||||
|
return -EAGAIN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Found on ndiswrapper dumps */
|
||||||
|
var_pattern = 0x003b080f;
|
||||||
|
ath5k_hw_reg_write(ah, var_pattern, cur_reg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Check if the device is supported and initialize the needed structs
|
* Check if the device is supported and initialize the needed structs
|
||||||
*/
|
*/
|
||||||
struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
|
struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
|
||||||
{
|
{
|
||||||
struct ath5k_hw *ah;
|
struct ath5k_hw *ah;
|
||||||
|
struct pci_dev *pdev = sc->pdev;
|
||||||
u8 mac[ETH_ALEN];
|
u8 mac[ETH_ALEN];
|
||||||
int ret;
|
int ret;
|
||||||
u32 srev;
|
u32 srev;
|
||||||
@ -204,10 +262,13 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
|
|||||||
CHANNEL_2GHZ);
|
CHANNEL_2GHZ);
|
||||||
|
|
||||||
/* Return on unsuported chips (unsupported eeprom etc) */
|
/* Return on unsuported chips (unsupported eeprom etc) */
|
||||||
if (srev >= AR5K_SREV_VER_AR5416) {
|
if ((srev >= AR5K_SREV_VER_AR5416) &&
|
||||||
|
(srev < AR5K_SREV_VER_AR2425)) {
|
||||||
ATH5K_ERR(sc, "Device not yet supported.\n");
|
ATH5K_ERR(sc, "Device not yet supported.\n");
|
||||||
ret = -ENODEV;
|
ret = -ENODEV;
|
||||||
goto err_free;
|
goto err_free;
|
||||||
|
} else if (srev == AR5K_SREV_VER_AR2425) {
|
||||||
|
ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Identify single chip solutions */
|
/* Identify single chip solutions */
|
||||||
@ -251,14 +312,57 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
|
|||||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
|
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
|
||||||
else
|
else
|
||||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
|
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
|
||||||
|
/*
|
||||||
} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
|
* Register returns 0x4 for radio revision
|
||||||
|
* so ath5k_hw_radio_revision doesn't parse the value
|
||||||
|
* correctly. For now we are based on mac's srev to
|
||||||
|
* identify RF2425 radio.
|
||||||
|
*/
|
||||||
|
} else if (srev == AR5K_SREV_VER_AR2425) {
|
||||||
ah->ah_radio = AR5K_RF2425;
|
ah->ah_radio = AR5K_RF2425;
|
||||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
|
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
|
||||||
}
|
}
|
||||||
|
|
||||||
ah->ah_phy = AR5K_PHY(0);
|
ah->ah_phy = AR5K_PHY(0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Identify AR5212-based PCI-E cards
|
||||||
|
* And write some initial settings.
|
||||||
|
*
|
||||||
|
* (doing a "strings" on ndis driver
|
||||||
|
* -ar5211.sys- reveals the following
|
||||||
|
* pci-e related functions:
|
||||||
|
*
|
||||||
|
* pcieClockReq
|
||||||
|
* pcieRxErrNotify
|
||||||
|
* pcieL1SKPEnable
|
||||||
|
* pcieAspm
|
||||||
|
* pcieDisableAspmOnRfWake
|
||||||
|
* pciePowerSaveEnable
|
||||||
|
*
|
||||||
|
* I guess these point to ClockReq but
|
||||||
|
* i'm not sure.)
|
||||||
|
*/
|
||||||
|
if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
|
||||||
|
ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
|
||||||
|
ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* POST
|
||||||
|
*/
|
||||||
|
ret = ath5k_hw_post(ah);
|
||||||
|
if (ret)
|
||||||
|
goto err_free;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Get card capabilities, values, ...
|
* Get card capabilities, values, ...
|
||||||
*/
|
*/
|
||||||
@ -2851,15 +2955,19 @@ int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
|
|||||||
* Update mib counters (statistics)
|
* Update mib counters (statistics)
|
||||||
*/
|
*/
|
||||||
void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
|
void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
|
||||||
struct ath5k_mib_stats *statistics)
|
struct ieee80211_low_level_stats *stats)
|
||||||
{
|
{
|
||||||
ATH5K_TRACE(ah->ah_sc);
|
ATH5K_TRACE(ah->ah_sc);
|
||||||
|
|
||||||
/* Read-And-Clear */
|
/* Read-And-Clear */
|
||||||
statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
|
stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
|
||||||
statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
|
stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
|
||||||
statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
|
stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
|
||||||
statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
|
stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
|
||||||
statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
|
|
||||||
|
/* XXX: Should we use this to track beacon count ?
|
||||||
|
* -we read it anyway to clear the register */
|
||||||
|
ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
|
||||||
|
|
||||||
/* Reset profile count registers on 5212*/
|
/* Reset profile count registers on 5212*/
|
||||||
if (ah->ah_version == AR5K_AR5212) {
|
if (ah->ah_version == AR5K_AR5212) {
|
||||||
@ -2960,8 +3068,16 @@ int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
|
|||||||
for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
|
for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
|
||||||
ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
|
ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
|
||||||
|
|
||||||
/* Set NULL encryption on non-5210*/
|
/*
|
||||||
if (ah->ah_version != AR5K_AR5210)
|
* Set NULL encryption on AR5212+
|
||||||
|
*
|
||||||
|
* Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
|
||||||
|
* AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
|
||||||
|
*
|
||||||
|
* Note2: Windows driver (ndiswrapper) sets this to
|
||||||
|
* 0x00000714 instead of 0x00000007
|
||||||
|
*/
|
||||||
|
if (ah->ah_version > AR5K_AR5211)
|
||||||
ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
|
ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
|
||||||
AR5K_KEYTABLE_TYPE(entry));
|
AR5K_KEYTABLE_TYPE(entry));
|
||||||
|
|
||||||
|
|||||||
@ -1,121 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
|
|
||||||
*
|
|
||||||
* Permission to use, copy, modify, and distribute this software for any
|
|
||||||
* purpose with or without fee is hereby granted, provided that the above
|
|
||||||
* copyright notice and this permission notice appear in all copies.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Basic regulation domain extensions for the IEEE 802.11 stack
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/string.h>
|
|
||||||
|
|
||||||
#include "regdom.h"
|
|
||||||
|
|
||||||
static const struct ath5k_regdommap {
|
|
||||||
enum ath5k_regdom dmn;
|
|
||||||
enum ath5k_regdom dmn5;
|
|
||||||
enum ath5k_regdom dmn2;
|
|
||||||
} r_map[] = {
|
|
||||||
{ DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG },
|
|
||||||
{ DMN_NULL_WORLD, DMN_NULL, DMN_WORLD },
|
|
||||||
{ DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB },
|
|
||||||
{ DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC },
|
|
||||||
{ DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA },
|
|
||||||
{ DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD },
|
|
||||||
{ DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA },
|
|
||||||
{ DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD },
|
|
||||||
{ DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC },
|
|
||||||
{ DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 },
|
|
||||||
{ DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD },
|
|
||||||
{ DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD },
|
|
||||||
{ DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD },
|
|
||||||
{ DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD },
|
|
||||||
{ DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD },
|
|
||||||
{ DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD },
|
|
||||||
{ DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC },
|
|
||||||
{ DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD },
|
|
||||||
{ DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD },
|
|
||||||
{ DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 },
|
|
||||||
{ DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA },
|
|
||||||
{ DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA },
|
|
||||||
{ DMN_APL4_WORLD, DMN_APL4, DMN_WORLD },
|
|
||||||
{ DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA },
|
|
||||||
{ DMN_APL_NULL, DMN_APL1, DMN_NULL },
|
|
||||||
{ DMN_APL2_WORLD, DMN_APL2, DMN_WORLD },
|
|
||||||
{ DMN_APL2_APLC, DMN_APL2, DMN_WORLD },
|
|
||||||
{ DMN_APL3_WORLD, DMN_APL3, DMN_WORLD },
|
|
||||||
{ DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA },
|
|
||||||
{ DMN_APL2_APLD, DMN_APL2, DMN_APLD },
|
|
||||||
{ DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA },
|
|
||||||
{ DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA },
|
|
||||||
{ DMN_APL1_WORLD, DMN_APL1, DMN_WORLD },
|
|
||||||
{ DMN_APL1_FCCA, DMN_APL1, DMN_FCCA },
|
|
||||||
{ DMN_APL1_APLA, DMN_APL1, DMN_WORLD },
|
|
||||||
{ DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC },
|
|
||||||
{ DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC },
|
|
||||||
{ DMN_APL5_WORLD, DMN_APL5, DMN_WORLD },
|
|
||||||
{ DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD },
|
|
||||||
{ DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
{ DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD },
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom dmn, u16 mhz)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(r_map); i++) {
|
|
||||||
if (r_map[i].dmn == dmn) {
|
|
||||||
if (mhz >= 2000 && mhz <= 3000)
|
|
||||||
return r_map[i].dmn2;
|
|
||||||
if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN &&
|
|
||||||
mhz <= IEEE80211_CHANNELS_5GHZ_MAX)
|
|
||||||
return r_map[i].dmn5;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return DMN_DEBUG;
|
|
||||||
}
|
|
||||||
|
|
||||||
u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee)
|
|
||||||
{
|
|
||||||
u32 regdomain = (u32)ieee;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use the default regulation domain if the value is empty
|
|
||||||
* or not supported by the net80211 regulation code.
|
|
||||||
*/
|
|
||||||
if (ath5k_regdom2flag(regdomain, IEEE80211_CHANNELS_5GHZ_MIN) ==
|
|
||||||
DMN_DEBUG)
|
|
||||||
return (u16)AR5K_TUNE_REGDOMAIN;
|
|
||||||
|
|
||||||
/* It is supported, just return the value */
|
|
||||||
return regdomain;
|
|
||||||
}
|
|
||||||
|
|
||||||
enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain)
|
|
||||||
{
|
|
||||||
enum ath5k_regdom ieee = (enum ath5k_regdom)regdomain;
|
|
||||||
|
|
||||||
return ieee;
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,500 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
|
|
||||||
*
|
|
||||||
* Permission to use, copy, modify, and distribute this software for any
|
|
||||||
* purpose with or without fee is hereby granted, provided that the above
|
|
||||||
* copyright notice and this permission notice appear in all copies.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _IEEE80211_REGDOMAIN_H_
|
|
||||||
#define _IEEE80211_REGDOMAIN_H_
|
|
||||||
|
|
||||||
#include <linux/types.h>
|
|
||||||
|
|
||||||
/* Default regulation domain if stored value EEPROM value is invalid */
|
|
||||||
#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */
|
|
||||||
#define AR5K_TUNE_CTRY CTRY_DEFAULT
|
|
||||||
|
|
||||||
|
|
||||||
enum ath5k_regdom {
|
|
||||||
DMN_DEFAULT = 0x00,
|
|
||||||
DMN_NULL_WORLD = 0x03,
|
|
||||||
DMN_NULL_ETSIB = 0x07,
|
|
||||||
DMN_NULL_ETSIC = 0x08,
|
|
||||||
DMN_FCC1_FCCA = 0x10,
|
|
||||||
DMN_FCC1_WORLD = 0x11,
|
|
||||||
DMN_FCC2_FCCA = 0x20,
|
|
||||||
DMN_FCC2_WORLD = 0x21,
|
|
||||||
DMN_FCC2_ETSIC = 0x22,
|
|
||||||
DMN_FRANCE_NULL = 0x31,
|
|
||||||
DMN_FCC3_FCCA = 0x3A,
|
|
||||||
DMN_ETSI1_WORLD = 0x37,
|
|
||||||
DMN_ETSI3_ETSIA = 0x32,
|
|
||||||
DMN_ETSI2_WORLD = 0x35,
|
|
||||||
DMN_ETSI3_WORLD = 0x36,
|
|
||||||
DMN_ETSI4_WORLD = 0x30,
|
|
||||||
DMN_ETSI4_ETSIC = 0x38,
|
|
||||||
DMN_ETSI5_WORLD = 0x39,
|
|
||||||
DMN_ETSI6_WORLD = 0x34,
|
|
||||||
DMN_ETSI_NULL = 0x33,
|
|
||||||
DMN_MKK1_MKKA = 0x40,
|
|
||||||
DMN_MKK1_MKKB = 0x41,
|
|
||||||
DMN_APL4_WORLD = 0x42,
|
|
||||||
DMN_MKK2_MKKA = 0x43,
|
|
||||||
DMN_APL_NULL = 0x44,
|
|
||||||
DMN_APL2_WORLD = 0x45,
|
|
||||||
DMN_APL2_APLC = 0x46,
|
|
||||||
DMN_APL3_WORLD = 0x47,
|
|
||||||
DMN_MKK1_FCCA = 0x48,
|
|
||||||
DMN_APL2_APLD = 0x49,
|
|
||||||
DMN_MKK1_MKKA1 = 0x4A,
|
|
||||||
DMN_MKK1_MKKA2 = 0x4B,
|
|
||||||
DMN_APL1_WORLD = 0x52,
|
|
||||||
DMN_APL1_FCCA = 0x53,
|
|
||||||
DMN_APL1_APLA = 0x54,
|
|
||||||
DMN_APL1_ETSIC = 0x55,
|
|
||||||
DMN_APL2_ETSIC = 0x56,
|
|
||||||
DMN_APL5_WORLD = 0x58,
|
|
||||||
DMN_WOR0_WORLD = 0x60,
|
|
||||||
DMN_WOR1_WORLD = 0x61,
|
|
||||||
DMN_WOR2_WORLD = 0x62,
|
|
||||||
DMN_WOR3_WORLD = 0x63,
|
|
||||||
DMN_WOR4_WORLD = 0x64,
|
|
||||||
DMN_WOR5_ETSIC = 0x65,
|
|
||||||
DMN_WOR01_WORLD = 0x66,
|
|
||||||
DMN_WOR02_WORLD = 0x67,
|
|
||||||
DMN_EU1_WORLD = 0x68,
|
|
||||||
DMN_WOR9_WORLD = 0x69,
|
|
||||||
DMN_WORA_WORLD = 0x6A,
|
|
||||||
|
|
||||||
DMN_APL1 = 0xf0000001,
|
|
||||||
DMN_APL2 = 0xf0000002,
|
|
||||||
DMN_APL3 = 0xf0000004,
|
|
||||||
DMN_APL4 = 0xf0000008,
|
|
||||||
DMN_APL5 = 0xf0000010,
|
|
||||||
DMN_ETSI1 = 0xf0000020,
|
|
||||||
DMN_ETSI2 = 0xf0000040,
|
|
||||||
DMN_ETSI3 = 0xf0000080,
|
|
||||||
DMN_ETSI4 = 0xf0000100,
|
|
||||||
DMN_ETSI5 = 0xf0000200,
|
|
||||||
DMN_ETSI6 = 0xf0000400,
|
|
||||||
DMN_ETSIA = 0xf0000800,
|
|
||||||
DMN_ETSIB = 0xf0001000,
|
|
||||||
DMN_ETSIC = 0xf0002000,
|
|
||||||
DMN_FCC1 = 0xf0004000,
|
|
||||||
DMN_FCC2 = 0xf0008000,
|
|
||||||
DMN_FCC3 = 0xf0010000,
|
|
||||||
DMN_FCCA = 0xf0020000,
|
|
||||||
DMN_APLD = 0xf0040000,
|
|
||||||
DMN_MKK1 = 0xf0080000,
|
|
||||||
DMN_MKK2 = 0xf0100000,
|
|
||||||
DMN_MKKA = 0xf0200000,
|
|
||||||
DMN_NULL = 0xf0400000,
|
|
||||||
DMN_WORLD = 0xf0800000,
|
|
||||||
DMN_DEBUG = 0xf1000000 /* used for debugging */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000)
|
|
||||||
|
|
||||||
enum ath5k_countrycode {
|
|
||||||
CTRY_DEFAULT = 0, /* Default domain (NA) */
|
|
||||||
CTRY_ALBANIA = 8, /* Albania */
|
|
||||||
CTRY_ALGERIA = 12, /* Algeria */
|
|
||||||
CTRY_ARGENTINA = 32, /* Argentina */
|
|
||||||
CTRY_ARMENIA = 51, /* Armenia */
|
|
||||||
CTRY_AUSTRALIA = 36, /* Australia */
|
|
||||||
CTRY_AUSTRIA = 40, /* Austria */
|
|
||||||
CTRY_AZERBAIJAN = 31, /* Azerbaijan */
|
|
||||||
CTRY_BAHRAIN = 48, /* Bahrain */
|
|
||||||
CTRY_BELARUS = 112, /* Belarus */
|
|
||||||
CTRY_BELGIUM = 56, /* Belgium */
|
|
||||||
CTRY_BELIZE = 84, /* Belize */
|
|
||||||
CTRY_BOLIVIA = 68, /* Bolivia */
|
|
||||||
CTRY_BRAZIL = 76, /* Brazil */
|
|
||||||
CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
|
|
||||||
CTRY_BULGARIA = 100, /* Bulgaria */
|
|
||||||
CTRY_CANADA = 124, /* Canada */
|
|
||||||
CTRY_CHILE = 152, /* Chile */
|
|
||||||
CTRY_CHINA = 156, /* People's Republic of China */
|
|
||||||
CTRY_COLOMBIA = 170, /* Colombia */
|
|
||||||
CTRY_COSTA_RICA = 188, /* Costa Rica */
|
|
||||||
CTRY_CROATIA = 191, /* Croatia */
|
|
||||||
CTRY_CYPRUS = 196, /* Cyprus */
|
|
||||||
CTRY_CZECH = 203, /* Czech Republic */
|
|
||||||
CTRY_DENMARK = 208, /* Denmark */
|
|
||||||
CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
|
|
||||||
CTRY_ECUADOR = 218, /* Ecuador */
|
|
||||||
CTRY_EGYPT = 818, /* Egypt */
|
|
||||||
CTRY_EL_SALVADOR = 222, /* El Salvador */
|
|
||||||
CTRY_ESTONIA = 233, /* Estonia */
|
|
||||||
CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
|
|
||||||
CTRY_FINLAND = 246, /* Finland */
|
|
||||||
CTRY_FRANCE = 250, /* France */
|
|
||||||
CTRY_FRANCE2 = 255, /* France2 */
|
|
||||||
CTRY_GEORGIA = 268, /* Georgia */
|
|
||||||
CTRY_GERMANY = 276, /* Germany */
|
|
||||||
CTRY_GREECE = 300, /* Greece */
|
|
||||||
CTRY_GUATEMALA = 320, /* Guatemala */
|
|
||||||
CTRY_HONDURAS = 340, /* Honduras */
|
|
||||||
CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
|
|
||||||
CTRY_HUNGARY = 348, /* Hungary */
|
|
||||||
CTRY_ICELAND = 352, /* Iceland */
|
|
||||||
CTRY_INDIA = 356, /* India */
|
|
||||||
CTRY_INDONESIA = 360, /* Indonesia */
|
|
||||||
CTRY_IRAN = 364, /* Iran */
|
|
||||||
CTRY_IRAQ = 368, /* Iraq */
|
|
||||||
CTRY_IRELAND = 372, /* Ireland */
|
|
||||||
CTRY_ISRAEL = 376, /* Israel */
|
|
||||||
CTRY_ITALY = 380, /* Italy */
|
|
||||||
CTRY_JAMAICA = 388, /* Jamaica */
|
|
||||||
CTRY_JAPAN = 392, /* Japan */
|
|
||||||
CTRY_JAPAN1 = 393, /* Japan (JP1) */
|
|
||||||
CTRY_JAPAN2 = 394, /* Japan (JP0) */
|
|
||||||
CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
|
|
||||||
CTRY_JAPAN4 = 396, /* Japan (JE1) */
|
|
||||||
CTRY_JAPAN5 = 397, /* Japan (JE2) */
|
|
||||||
CTRY_JORDAN = 400, /* Jordan */
|
|
||||||
CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
|
|
||||||
CTRY_KENYA = 404, /* Kenya */
|
|
||||||
CTRY_KOREA_NORTH = 408, /* North Korea */
|
|
||||||
CTRY_KOREA_ROC = 410, /* South Korea */
|
|
||||||
CTRY_KOREA_ROC2 = 411, /* South Korea */
|
|
||||||
CTRY_KUWAIT = 414, /* Kuwait */
|
|
||||||
CTRY_LATVIA = 428, /* Latvia */
|
|
||||||
CTRY_LEBANON = 422, /* Lebanon */
|
|
||||||
CTRY_LIBYA = 434, /* Libya */
|
|
||||||
CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
|
|
||||||
CTRY_LITHUANIA = 440, /* Lithuania */
|
|
||||||
CTRY_LUXEMBOURG = 442, /* Luxembourg */
|
|
||||||
CTRY_MACAU = 446, /* Macau */
|
|
||||||
CTRY_MACEDONIA = 807, /* Republic of Macedonia */
|
|
||||||
CTRY_MALAYSIA = 458, /* Malaysia */
|
|
||||||
CTRY_MEXICO = 484, /* Mexico */
|
|
||||||
CTRY_MONACO = 492, /* Principality of Monaco */
|
|
||||||
CTRY_MOROCCO = 504, /* Morocco */
|
|
||||||
CTRY_NETHERLANDS = 528, /* Netherlands */
|
|
||||||
CTRY_NEW_ZEALAND = 554, /* New Zealand */
|
|
||||||
CTRY_NICARAGUA = 558, /* Nicaragua */
|
|
||||||
CTRY_NORWAY = 578, /* Norway */
|
|
||||||
CTRY_OMAN = 512, /* Oman */
|
|
||||||
CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
|
|
||||||
CTRY_PANAMA = 591, /* Panama */
|
|
||||||
CTRY_PARAGUAY = 600, /* Paraguay */
|
|
||||||
CTRY_PERU = 604, /* Peru */
|
|
||||||
CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
|
|
||||||
CTRY_POLAND = 616, /* Poland */
|
|
||||||
CTRY_PORTUGAL = 620, /* Portugal */
|
|
||||||
CTRY_PUERTO_RICO = 630, /* Puerto Rico */
|
|
||||||
CTRY_QATAR = 634, /* Qatar */
|
|
||||||
CTRY_ROMANIA = 642, /* Romania */
|
|
||||||
CTRY_RUSSIA = 643, /* Russia */
|
|
||||||
CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
|
|
||||||
CTRY_SINGAPORE = 702, /* Singapore */
|
|
||||||
CTRY_SLOVAKIA = 703, /* Slovak Republic */
|
|
||||||
CTRY_SLOVENIA = 705, /* Slovenia */
|
|
||||||
CTRY_SOUTH_AFRICA = 710, /* South Africa */
|
|
||||||
CTRY_SPAIN = 724, /* Spain */
|
|
||||||
CTRY_SRI_LANKA = 728, /* Sri Lanka */
|
|
||||||
CTRY_SWEDEN = 752, /* Sweden */
|
|
||||||
CTRY_SWITZERLAND = 756, /* Switzerland */
|
|
||||||
CTRY_SYRIA = 760, /* Syria */
|
|
||||||
CTRY_TAIWAN = 158, /* Taiwan */
|
|
||||||
CTRY_THAILAND = 764, /* Thailand */
|
|
||||||
CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
|
|
||||||
CTRY_TUNISIA = 788, /* Tunisia */
|
|
||||||
CTRY_TURKEY = 792, /* Turkey */
|
|
||||||
CTRY_UAE = 784, /* U.A.E. */
|
|
||||||
CTRY_UKRAINE = 804, /* Ukraine */
|
|
||||||
CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
|
|
||||||
CTRY_UNITED_STATES = 840, /* United States */
|
|
||||||
CTRY_URUGUAY = 858, /* Uruguay */
|
|
||||||
CTRY_UZBEKISTAN = 860, /* Uzbekistan */
|
|
||||||
CTRY_VENEZUELA = 862, /* Venezuela */
|
|
||||||
CTRY_VIET_NAM = 704, /* Viet Nam */
|
|
||||||
CTRY_YEMEN = 887, /* Yemen */
|
|
||||||
CTRY_ZIMBABWE = 716, /* Zimbabwe */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */
|
|
||||||
#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */
|
|
||||||
#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */
|
|
||||||
#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */
|
|
||||||
|
|
||||||
struct ath5k_regchannel {
|
|
||||||
u16 chan;
|
|
||||||
enum ath5k_regdom domain;
|
|
||||||
u32 mode;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IEEE80211_CHANNELS_2GHZ { \
|
|
||||||
/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \
|
|
||||||
\
|
|
||||||
/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define IEEE80211_CHANNELS_5GHZ { \
|
|
||||||
/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \
|
|
||||||
/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \
|
|
||||||
/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \
|
|
||||||
/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \
|
|
||||||
/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \
|
|
||||||
/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \
|
|
||||||
/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \
|
|
||||||
/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \
|
|
||||||
/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
|
||||||
/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \
|
|
||||||
/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \
|
|
||||||
/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \
|
|
||||||
/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \
|
|
||||||
\
|
|
||||||
/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \
|
|
||||||
/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \
|
|
||||||
/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \
|
|
||||||
/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \
|
|
||||||
}
|
|
||||||
|
|
||||||
enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom, u16);
|
|
||||||
u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee);
|
|
||||||
enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in New Issue
Block a user