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clk: mediatek: reset: add infra_ao reset support for MT8188

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The infra_ao reset is needed for MT8188.
- Add mtk_clk_rst_desc for MT8188.
- Add register reset controller function for MT8188 infra_ao.
- Add infra_ao_idx_map for MT8188.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230525075011.7032-3-runyang.chen@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Runyang Chen 2023-05-25 15:50:11 +08:00 committed by Stephen Boyd
parent 2cf4ec5344
commit 18eb864f1a
1 changed files with 24 additions and 0 deletions
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24
drivers/clk/mediatek/clk-mt8188-infra_ao.c
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@ -5,6 +5,7 @@
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/reset/mt8188-resets.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] = {
"infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
};
static u16 infra_ao_rst_ofs[] = {
INFRA_RST0_SET_OFFSET,
INFRA_RST1_SET_OFFSET,
INFRA_RST2_SET_OFFSET,
INFRA_RST3_SET_OFFSET,
INFRA_RST4_SET_OFFSET,
};
static u16 infra_ao_idx_map[] = {
[MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2,
[MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4,
[MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
};
static const struct mtk_clk_rst_desc infra_ao_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_ao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
.rst_idx_map = infra_ao_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
.rst_desc = &infra_ao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {