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drm/radeon: enable SRBM timeout interrupt on SI

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Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2015-02-18 13:19:27 +01:00 committed by Alex Deucher
parent dc12a3ec71
commit 18ad01effe
2 changed files with 11 additions and 0 deletions
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7
drivers/gpu/drm/radeon/si.c
View File

@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev)
} }
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
WREG32(SRBM_INT_CNTL, 1);
WREG32(SRBM_INT_ACK, 1);
evergreen_fix_pci_max_read_req_size(rdev); evergreen_fix_pci_max_read_req_size(rdev);
@ -5911,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
WREG32(GRBM_INT_CNTL, 0); WREG32(GRBM_INT_CNTL, 0);
WREG32(SRBM_INT_CNTL, 0);
if (rdev->num_crtc >= 2) { if (rdev->num_crtc >= 2) {
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@ -6610,6 +6613,10 @@ restart_ih:
break; break;
} }
break; break;
case 96:
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
WREG32(SRBM_INT_ACK, 0x1);
break;
case 124: /* UVD */ case 124: /* UVD */
DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);

4
drivers/gpu/drm/radeon/sid.h
View File

@ -358,6 +358,10 @@
#define CC_SYS_RB_BACKEND_DISABLE 0xe80 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
#define SRBM_READ_ERROR 0xE98
#define SRBM_INT_CNTL 0xEA0
#define SRBM_INT_ACK 0xEA8
#define SRBM_STATUS2 0x0EC4 #define SRBM_STATUS2 0x0EC4
#define DMA_BUSY (1 << 5) #define DMA_BUSY (1 << 5)
#define DMA1_BUSY (1 << 6) #define DMA1_BUSY (1 << 6)