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gma500: Final polish
This completes the clean up all the non Medfield C files to the point where checkpatch approves of them barring some silly 80 column whining. The Medfield stuff is still in a lot of flux but the rest is now ready for general tidy and review. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -756,10 +756,10 @@ static void psb_setup_outputs(struct drm_device *dev)
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clone_mask = (1 << INTEL_OUTPUT_MIPI2);
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break;
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case INTEL_OUTPUT_HDMI:
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if (IS_MFLD(dev))
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crtc_mask = (1 << 1);
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else /* FIXME: review Oaktrail */
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crtc_mask = (1 << 0); /* Cedarview */
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if (IS_MFLD(dev))
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crtc_mask = (1 << 1);
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else /* FIXME: review Oaktrail */
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crtc_mask = (1 << 0); /* Cedarview */
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clone_mask = (1 << INTEL_OUTPUT_HDMI);
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break;
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}
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@ -398,7 +398,7 @@ int psb_gtt_init(struct drm_device *dev, int resume)
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dev_priv->gtt_initialized = 1;
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pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
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/*
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* FIXME: video mmu has hw bug to access 0x0D0000000,
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* then make gatt start at 0x0e000,0000
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@ -347,6 +347,6 @@ const struct psb_ops psb_chip_ops = {
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.save_regs = psb_save_display_registers,
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.restore_regs = psb_restore_display_registers,
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.power_down = psb_power_down,
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.power_up = psb_power_up,
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.power_up = psb_power_up,
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};
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@ -52,7 +52,7 @@ module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
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static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
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{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
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{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
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#if defined(CONFIG_DRM_PSB_MRST)
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#if defined(CONFIG_DRM_PSB_MRST)
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{ 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
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{ 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
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{ 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
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@ -72,7 +72,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
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{ 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
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{ 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
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#endif
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#if defined(CONFIG_DRM_PSB_CDV)
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#if defined(CONFIG_DRM_PSB_CDV)
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{ 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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{ 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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{ 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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@ -81,7 +81,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
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{ 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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{ 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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{ 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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#endif
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#endif
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{ 0, 0, 0}
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};
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MODULE_DEVICE_TABLE(pci, pciidlist);
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@ -409,7 +409,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
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#ifdef CONFIG_MDFLD_DSI_DPU
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/*init dpu info*/
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mdfld_dbi_dpu_init(dev);
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#else
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#else
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mdfld_dbi_dsr_init(dev);
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#endif /*CONFIG_MDFLD_DSI_DPU*/
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/* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/
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@ -1284,9 +1284,9 @@ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
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*/
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static void psb_intel_cursor_init(struct drm_device *dev, int pipe)
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{
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u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
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u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
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u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
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u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
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REG_WRITE(control[pipe], 0);
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REG_WRITE(base[pipe], 0);
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}
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@ -1341,7 +1341,7 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe,
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psb_intel_crtc->cursor_addr = 0;
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drm_crtc_helper_add(&psb_intel_crtc->base,
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dev_priv->ops->crtc_helper);
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dev_priv->ops->crtc_helper);
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/* Setup the array of drm_connector pointer array */
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psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
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