Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-23 20:51:44 +00:00
Code Issues Packages Projects Releases Wiki Activity

clk: tegra: Changes for v5.6-rc1

Browse Source 
This contains some minor fixes and cleanups for Tegra clocks.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl4u3osTHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zodMKD/435mioQ2sTWjWliqWXOWfGYgiM9UhJ
 h9+nIyhX2g45m4zNJkgCwOUY9pIMA+wQmUziQuux3jEiEmODT82hYESYJFyoIOjC
 zFLZeNMjMS6vTF2nXH9RhrqxyI2fJpkudPmuuDMdwracS3Uxc7pnX8bPwZQBlfOM
 OSxZNdHMChBIRbo5Az4ZHBl4mEDhc/UnklEd/vV9CBWSfMGK4FgBUS7a9vIC1R2/
 dRW5tZXkZ3SzdJ+yCps/iBQBl5oqlOUCcqgnBKDnXjD1LCz1tSb+lqgVQBn4iHh3
 javY/2gy+ecU3e7eFNxdMmV83tu4EFf/bgOKaMnx05eU9PcpxYGhi3GdXIWZ9WWl
 DLZ/Af4Sl6qNT1ZA37NvyTPqHFiYU0ogpEFISQBaaM7IZV9Zilfq0KKlYMfL4wnn
 6saVnb8ixE4cBC/bHR2X0D8185OTxHvlB7t78qhPnQJiSDq3VILMZwJ3stB5KLGI
 a+vNbFnjfpOnIRXmSOmNXVhyae6Ih9Ou3H46uo1soScYIEh/cMU2f/jLvJpFBRFX
 2Pwv5KRnVkBHxSJfDMePGCMkXzzsQiGPMwVtdy9lqR//0F0TUCSpiE6qNjY7/xNa
 CBgPlV79YGMZUDeUzU86KBfWDB3P+CCsoEG9YSccNlUgpRnIKCQg5SQpdmV/QJD2
 R3RnTKykq1NJSg==
 =1TiK
 -----END PGP SIGNATURE-----

Merge tag 'for-5.6-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia

Pull Nvidia Tegra clk driver updates from Thierry Reding

* tag 'for-5.6-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra20/30: Explicitly set parent clock for Video Decoder
  clk: tegra20/30: Don't pre-initialize displays parent clock
  clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
  clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
  clk: tegra: Mark fuse clock as critical
This commit is contained in:
Stephen Boyd 2020-01-27 11:00:24 -08:00
commit 185dfe32d7
5 changed files with 15 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/clk/tegra/clk-dfll.c
View File

@ -1487,7 +1487,6 @@ static int dfll_init(struct tegra_dfll *td)
td->last_unrounded_rate = 0;
pm_runtime_enable(td->dev);
pm_runtime_irq_safe(td->dev);
pm_runtime_get_sync(td->dev);
dfll_set_mode(td, DFLL_DISABLED);
@ -1516,7 +1515,7 @@ di_err1:
/**
* tegra_dfll_suspend - check DFLL is disabled
* @dev: DFLL device *
* @dev: DFLL instance
*
* DFLL clock should be disabled by the CPUFreq driver. So, make
* sure it is disabled and disable all clocks needed by the DFLL.

9
drivers/clk/tegra/clk-divider.c
View File

@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
int div, mul;
u64 rate = parent_rate;
reg = readl_relaxed(divider->reg) >> divider->shift;
div = reg & div_mask(divider);
reg = readl_relaxed(divider->reg);
if ((divider->flags & TEGRA_DIVIDER_UART) &&
!(reg & PERIPH_CLK_UART_DIV_ENB))
return rate;
div = (reg >> divider->shift) & div_mask(divider);
mul = get_mul(divider);
div += mul;

6
drivers/clk/tegra/clk-tegra-periph.c
View File

@ -777,7 +777,11 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
/*
* Critical for RAM re-repair operation, which must occur on resume
* from LP1 system suspend and as part of CCPLEX cluster switching.
*/
GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),

4
drivers/clk/tegra/clk-tegra20.c
View File

@ -1046,11 +1046,9 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
{ TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
{ TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
{ TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
/* must be the last entry */
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
};

4
drivers/clk/tegra/clk-tegra30.c
View File

@ -1251,14 +1251,12 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
{ TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
{ TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
{ TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
{ TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
{ TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
{ TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
{ TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 },
{ TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
{ TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
{ TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },