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[SPARC64]: First cut at SUN4V PCI IOMMU handling.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
164c220fa3
commit
1839794464
@ -562,7 +562,7 @@ static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int n
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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pci_map_single(pdev,
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pci_4u_map_single(pdev,
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(page_address(sglist->page) + sglist->offset),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
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@ -9,6 +9,7 @@
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <asm/pbm.h>
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#include <asm/iommu.h>
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@ -23,39 +24,481 @@
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#include "pci_sun4v.h"
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#define PGLIST_NENTS 2048
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struct sun4v_pglist {
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u64 pglist[PGLIST_NENTS];
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};
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static DEFINE_PER_CPU(struct sun4v_pglist, iommu_pglists);
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static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages)
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{
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unsigned long n, i, start, end, limit;
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int pass;
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limit = arena->limit;
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start = arena->hint;
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pass = 0;
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again:
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n = find_next_zero_bit(arena->map, limit, start);
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end = n + npages;
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if (unlikely(end >= limit)) {
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if (likely(pass < 1)) {
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limit = start;
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start = 0;
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pass++;
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goto again;
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} else {
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/* Scanned the whole thing, give up. */
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return -1;
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}
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}
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for (i = n; i < end; i++) {
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if (test_bit(i, arena->map)) {
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start = i + 1;
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goto again;
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}
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}
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for (i = n; i < end; i++)
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__set_bit(i, arena->map);
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arena->hint = end;
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return n;
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}
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static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
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{
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unsigned long i;
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for (i = base; i < (base + npages); i++)
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__clear_bit(i, arena->map);
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}
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static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long devhandle, flags, order, first_page, npages, n;
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void *ret;
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long entry;
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u64 *pglist;
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int cpu;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (order >= MAX_ORDER)
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return NULL;
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npages = size >> IO_PAGE_SHIFT;
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if (npages > PGLIST_NENTS)
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return NULL;
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first_page = __get_free_pages(GFP_ATOMIC, order);
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if (first_page == 0UL)
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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pcp = pdev->sysdata;
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devhandle = pcp->pbm->devhandle;
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iommu = pcp->pbm->iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = pci_arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L)) {
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free_pages(first_page, order);
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return NULL;
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}
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*dma_addrp = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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first_page = __pa(first_page);
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cpu = get_cpu();
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pglist = &__get_cpu_var(iommu_pglists).pglist[0];
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for (n = 0; n < npages; n++)
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pglist[n] = first_page + (n * PAGE_SIZE);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
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npages,
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(HV_PCI_MAP_ATTR_READ |
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HV_PCI_MAP_ATTR_WRITE),
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__pa(pglist));
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entry += num;
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npages -= num;
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pglist += num;
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} while (npages != 0);
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put_cpu();
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return ret;
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}
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static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, order, npages, entry, devhandle;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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pci_arena_free(&iommu->arena, entry, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
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{
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return 0;
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr, devhandle;
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u32 bus_addr, ret;
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unsigned long prot;
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long entry;
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u64 *pglist;
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int cpu;
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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if (unlikely(direction == PCI_DMA_NONE))
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goto bad;
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oaddr = (unsigned long)ptr;
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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if (unlikely(npages > PGLIST_NENTS))
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goto bad;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = pci_arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != PCI_DMA_TODEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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cpu = get_cpu();
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pglist = &__get_cpu_var(iommu_pglists).pglist[0];
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for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE)
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pglist[i] = base_paddr;
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do {
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unsigned long num;
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num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
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npages, prot,
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__pa(pglist));
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entry += num;
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npages -= num;
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pglist += num;
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} while (npages != 0);
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put_cpu();
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return ret;
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return PCI_DMA_ERROR_CODE;
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}
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static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, npages, devhandle;
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long entry;
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if (unlikely(direction == PCI_DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return;
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}
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
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pci_arena_free(&iommu->arena, entry, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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#define SG_ENT_PHYS_ADDRESS(SG) \
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(__pa(page_address((SG)->page)) + (SG)->offset)
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static inline void fill_sg(long entry, unsigned long devhandle,
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struct scatterlist *sg,
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int nused, int nelems, unsigned long prot)
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{
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struct scatterlist *dma_sg = sg;
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struct scatterlist *sg_end = sg + nelems;
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int i, cpu, pglist_ent;
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u64 *pglist;
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cpu = get_cpu();
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pglist = &__get_cpu_var(iommu_pglists).pglist[0];
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pglist_ent = 0;
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for (i = 0; i < nused; i++) {
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unsigned long pteval = ~0UL;
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u32 dma_npages;
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dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
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dma_sg->dma_length +
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((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
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do {
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unsigned long offset;
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signed int len;
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/* If we are here, we know we have at least one
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* more page to map. So walk forward until we
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* hit a page crossing, and begin creating new
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* mappings from that spot.
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*/
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for (;;) {
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unsigned long tmp;
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tmp = SG_ENT_PHYS_ADDRESS(sg);
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len = sg->length;
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if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = tmp & IO_PAGE_MASK;
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offset = tmp & (IO_PAGE_SIZE - 1UL);
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break;
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}
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if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
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offset = 0UL;
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len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
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break;
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}
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sg++;
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}
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pteval = (pteval & IOPTE_PAGE);
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while (len > 0) {
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pglist[pglist_ent++] = pteval;
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pteval += IO_PAGE_SIZE;
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len -= (IO_PAGE_SIZE - offset);
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offset = 0;
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dma_npages--;
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}
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pteval = (pteval & IOPTE_PAGE) + len;
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sg++;
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/* Skip over any tail mappings we've fully mapped,
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* adjusting pteval along the way. Stop when we
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* detect a page crossing event.
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*/
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while (sg < sg_end &&
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(pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
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(pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
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((pteval ^
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(SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
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pteval += sg->length;
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sg++;
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}
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if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
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pteval = ~0UL;
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} while (dma_npages != 0);
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dma_sg++;
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}
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BUG_ON(pglist_ent == 0);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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pglist_ent);
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entry += num;
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pglist_ent -= num;
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} while (pglist_ent != 0);
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put_cpu();
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}
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static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
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{
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return nelems;
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, npages, prot, devhandle;
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u32 dma_base;
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struct scatterlist *sgtmp;
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long entry;
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int used;
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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pci_4v_map_single(pdev,
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(page_address(sglist->page) + sglist->offset),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
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return 0;
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sglist->dma_length = sglist->length;
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return 1;
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}
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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if (unlikely(direction == PCI_DMA_NONE))
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goto bad;
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/* Step 1: Prepare scatter list. */
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npages = prepare_sg(sglist, nelems);
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if (unlikely(npages > PGLIST_NENTS))
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goto bad;
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/* Step 2: Allocate a cluster and context, if necessary. */
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spin_lock_irqsave(&iommu->lock, flags);
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entry = pci_arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto bad;
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dma_base = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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/* Step 3: Normalize DMA addresses. */
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used = nelems;
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sgtmp = sglist;
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while (used && sgtmp->dma_length) {
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sgtmp->dma_address += dma_base;
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sgtmp++;
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used--;
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}
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used = nelems - used;
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/* Step 4: Create the mappings. */
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != PCI_DMA_TODEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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fill_sg(entry, devhandle, sglist, used, nelems, prot);
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return used;
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return 0;
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}
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static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, i, npages, devhandle;
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long entry;
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u32 bus_addr;
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if (unlikely(direction == PCI_DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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}
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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bus_addr = sglist->dma_address & IO_PAGE_MASK;
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for (i = 1; i < nelems; i++)
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if (sglist[i].dma_length == 0)
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break;
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i--;
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npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
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bus_addr) >> IO_PAGE_SHIFT;
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entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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pci_arena_free(&iommu->arena, entry, npages);
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|
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
|
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|
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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|
||||
static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
|
||||
{
|
||||
/* Nothing to do... */
|
||||
}
|
||||
|
||||
static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
||||
{
|
||||
/* Nothing to do... */
|
||||
}
|
||||
|
||||
struct pci_iommu_ops pci_sun4v_iommu_ops = {
|
||||
@ -264,9 +707,83 @@ static void pbm_register_toplevel_resources(struct pci_controller_info *p,
|
||||
&pbm->mem_space);
|
||||
}
|
||||
|
||||
static void probe_existing_entries(struct pci_pbm_info *pbm,
|
||||
struct pci_iommu *iommu)
|
||||
{
|
||||
struct pci_iommu_arena *arena = &iommu->arena;
|
||||
unsigned long i, devhandle;
|
||||
|
||||
devhandle = pbm->devhandle;
|
||||
for (i = 0; i < arena->limit; i++) {
|
||||
unsigned long ret, io_attrs, ra;
|
||||
|
||||
ret = pci_sun4v_iommu_getmap(devhandle,
|
||||
HV_PCI_TSBID(0, i),
|
||||
&io_attrs, &ra);
|
||||
if (ret == HV_EOK)
|
||||
__set_bit(i, arena->map);
|
||||
}
|
||||
}
|
||||
|
||||
static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
|
||||
{
|
||||
/* XXX Implement me! XXX */
|
||||
struct pci_iommu *iommu = pbm->iommu;
|
||||
unsigned long num_tsb_entries, sz;
|
||||
u32 vdma[2], dma_mask, dma_offset;
|
||||
int err, tsbsize;
|
||||
|
||||
err = prom_getproperty(pbm->prom_node, "virtual-dma",
|
||||
(char *)&vdma[0], sizeof(vdma));
|
||||
if (err == 0 || err == -1) {
|
||||
/* No property, use default values. */
|
||||
vdma[0] = 0x80000000;
|
||||
vdma[1] = 0x80000000;
|
||||
}
|
||||
|
||||
dma_mask = vdma[0];
|
||||
switch (vdma[1]) {
|
||||
case 0x20000000:
|
||||
dma_mask |= 0x1fffffff;
|
||||
tsbsize = 64;
|
||||
break;
|
||||
|
||||
case 0x40000000:
|
||||
dma_mask |= 0x3fffffff;
|
||||
tsbsize = 128;
|
||||
break;
|
||||
|
||||
case 0x80000000:
|
||||
dma_mask |= 0x7fffffff;
|
||||
tsbsize = 128;
|
||||
break;
|
||||
|
||||
default:
|
||||
prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
|
||||
prom_halt();
|
||||
};
|
||||
|
||||
num_tsb_entries = tsbsize / sizeof(iopte_t);
|
||||
|
||||
dma_offset = vdma[0];
|
||||
|
||||
/* Setup initial software IOMMU state. */
|
||||
spin_lock_init(&iommu->lock);
|
||||
iommu->ctx_lowest_free = 1;
|
||||
iommu->page_table_map_base = dma_offset;
|
||||
iommu->dma_addr_mask = dma_mask;
|
||||
|
||||
/* Allocate and initialize the free area map. */
|
||||
sz = num_tsb_entries / 8;
|
||||
sz = (sz + 7UL) & ~7UL;
|
||||
iommu->arena.map = kmalloc(sz, GFP_KERNEL);
|
||||
if (!iommu->arena.map) {
|
||||
prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
memset(iommu->arena.map, 0, sz);
|
||||
iommu->arena.limit = num_tsb_entries;
|
||||
|
||||
probe_existing_entries(pbm, iommu);
|
||||
}
|
||||
|
||||
static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node)
|
||||
|
||||
@ -16,6 +16,10 @@ extern unsigned long pci_sun4v_iommu_map(unsigned long devhandle,
|
||||
extern unsigned long pci_sun4v_iommu_demap(unsigned long devhandle,
|
||||
unsigned long tsbid,
|
||||
unsigned long num_ttes);
|
||||
extern unsigned long pci_sun4v_iommu_getmap(unsigned long devhandle,
|
||||
unsigned long tsbid,
|
||||
unsigned long *io_attributes,
|
||||
unsigned long *real_address);
|
||||
extern unsigned long pci_sun4v_config_get(unsigned long devhandle,
|
||||
unsigned long pci_device,
|
||||
unsigned long config_offset,
|
||||
|
||||
@ -12,9 +12,7 @@
|
||||
*/
|
||||
.globl pci_sun4v_devino_to_sysino
|
||||
pci_sun4v_devino_to_sysino:
|
||||
mov %o1, %o2
|
||||
mov %o0, %o1
|
||||
mov HV_FAST_INTR_DEVINO2SYSINO, %o0
|
||||
mov HV_FAST_INTR_DEVINO2SYSINO, %o5
|
||||
ta HV_FAST_TRAP
|
||||
retl
|
||||
mov %o1, %o0
|
||||
@ -29,12 +27,7 @@ pci_sun4v_devino_to_sysino:
|
||||
*/
|
||||
.globl pci_sun4v_iommu_map
|
||||
pci_sun4v_iommu_map:
|
||||
mov %o4, %o5
|
||||
mov %o3, %o4
|
||||
mov %o2, %o3
|
||||
mov %o1, %o2
|
||||
mov %o0, %o1
|
||||
mov HV_FAST_PCI_IOMMU_MAP, %o0
|
||||
mov HV_FAST_PCI_IOMMU_MAP, %o5
|
||||
ta HV_FAST_TRAP
|
||||
retl
|
||||
mov %o1, %o0
|
||||
@ -47,14 +40,28 @@ pci_sun4v_iommu_map:
|
||||
*/
|
||||
.globl pci_sun4v_iommu_demap
|
||||
pci_sun4v_iommu_demap:
|
||||
mov %o2, %o3
|
||||
mov %o1, %o2
|
||||
mov %o0, %o1
|
||||
mov HV_FAST_PCI_IOMMU_DEMAP, %o0
|
||||
mov HV_FAST_PCI_IOMMU_DEMAP, %o5
|
||||
ta HV_FAST_TRAP
|
||||
retl
|
||||
mov %o1, %o0
|
||||
|
||||
/* %o0: devhandle
|
||||
* %o1: tsbid
|
||||
* %o2: &io_attributes
|
||||
* %o3: &real_address
|
||||
*
|
||||
* returns %o0: status
|
||||
*/
|
||||
.globl pci_sun4v_iommu_getmap
|
||||
pci_sun4v_iommu_getmap:
|
||||
mov %o2, %o4
|
||||
mov HV_FAST_PCI_IOMMU_GETMAP, %o5
|
||||
ta HV_FAST_TRAP
|
||||
stx %o1, [%o4]
|
||||
stx %o2, [%o3]
|
||||
retl
|
||||
mov %o0, %o0
|
||||
|
||||
/* %o0: devhandle
|
||||
* %o1: pci_device
|
||||
* %o2: pci_config_offset
|
||||
@ -67,11 +74,7 @@ pci_sun4v_iommu_demap:
|
||||
*/
|
||||
.globl pci_sun4v_config_get
|
||||
pci_sun4v_config_get:
|
||||
mov %o3, %o4
|
||||
mov %o2, %o3
|
||||
mov %o1, %o2
|
||||
mov %o0, %o1
|
||||
mov HV_FAST_PCI_CONFIG_GET, %o0
|
||||
mov HV_FAST_PCI_CONFIG_GET, %o5
|
||||
ta HV_FAST_TRAP
|
||||
brnz,a,pn %o1, 1f
|
||||
mov -1, %o2
|
||||
@ -91,14 +94,9 @@ pci_sun4v_config_get:
|
||||
*/
|
||||
.globl pci_sun4v_config_put
|
||||
pci_sun4v_config_put:
|
||||
mov %o3, %o4
|
||||
mov %o2, %o3
|
||||
mov %o1, %o2
|
||||
mov %o0, %o1
|
||||
mov HV_FAST_PCI_CONFIG_PUT, %o0
|
||||
mov HV_FAST_PCI_CONFIG_PUT, %o5
|
||||
ta HV_FAST_TRAP
|
||||
brnz,a,pn %o1, 1f
|
||||
mov -1, %o1
|
||||
1: retl
|
||||
mov %o1, %o0
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user