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ASoC: fsl_micfil: use GENMASK to define register bit fields
Use GENMASK along with FIELD_PREP and FIELD_GET to access bitfields in registers to straighten register access and to drop a lot of defines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Link: https://lore.kernel.org/r/20220414162249.3934543-6-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sascha Hauer
Mark Brown
parent
bd2cffd10d
commit
17f2142bae
@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright 2018 NXP
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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@ -116,23 +117,22 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
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int bclk;
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
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osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
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>> MICFIL_CTRL2_CICOSR_SHIFT);
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qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
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osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
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qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
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switch (qsel) {
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case MICFIL_HIGH_QUALITY:
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case MICFIL_QSEL_HIGH_QUALITY:
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bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
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break;
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case MICFIL_MEDIUM_QUALITY:
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case MICFIL_VLOW0_QUALITY:
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case MICFIL_QSEL_MEDIUM_QUALITY:
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case MICFIL_QSEL_VLOW0_QUALITY:
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bclk = rate * 4 * osr * 1; /* kfactor = 1 */
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break;
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case MICFIL_LOW_QUALITY:
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case MICFIL_VLOW1_QUALITY:
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case MICFIL_QSEL_LOW_QUALITY:
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case MICFIL_QSEL_VLOW1_QUALITY:
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bclk = rate * 2 * osr * 2; /* kfactor = 2 */
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break;
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case MICFIL_VLOW2_QUALITY:
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case MICFIL_QSEL_VLOW2_QUALITY:
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bclk = rate * osr * 4; /* kfactor = 4 */
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break;
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default:
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@ -244,8 +244,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
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* 11 - reserved
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*/
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_DISEL_MASK,
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(1 << MICFIL_CTRL1_DISEL_SHIFT));
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MICFIL_CTRL1_DISEL,
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FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
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if (ret) {
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dev_err(dev, "failed to update DISEL bits\n");
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return ret;
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@ -274,8 +274,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
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}
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_DISEL_MASK,
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(0 << MICFIL_CTRL1_DISEL_SHIFT));
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MICFIL_CTRL1_DISEL,
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FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
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if (ret) {
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dev_err(dev, "failed to update DISEL bits\n");
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return ret;
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@ -300,8 +300,8 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
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/* set CICOSR */
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ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_CICOSR_MASK,
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MICFIL_CTRL2_OSR_DEFAULT);
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MICFIL_CTRL2_CICOSR,
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FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
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if (ret)
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dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
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REG_MICFIL_CTRL2);
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@ -312,7 +312,8 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
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ret = -EINVAL;
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ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_CLKDIV_MASK, clk_div);
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MICFIL_CTRL2_CLKDIV,
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FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
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if (ret)
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dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
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REG_MICFIL_CTRL2);
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@ -368,13 +369,13 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
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{
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struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
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struct device *dev = cpu_dai->dev;
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unsigned int val;
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int ret;
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int i;
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/* set qsel to medium */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
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MICFIL_CTRL2_QSEL,
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FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
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if (ret) {
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dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
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REG_MICFIL_CTRL2);
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@ -390,10 +391,9 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
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&micfil->dma_params_rx);
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/* FIFO Watermark Control - FIFOWMK*/
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val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
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MICFIL_FIFO_CTRL_FIFOWMK_MASK,
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val);
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MICFIL_FIFO_CTRL_FIFOWMK,
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FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
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if (ret) {
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dev_err(dev, "failed to set FIFOWMK\n");
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return ret;
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@ -553,11 +553,11 @@ static irqreturn_t micfil_isr(int irq, void *devid)
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regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
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regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
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dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
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dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
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/* Channel 0-7 Output Data Flags */
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for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
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if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
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if (stat_reg & MICFIL_STAT_CHXF(i))
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dev_dbg(&pdev->dev,
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"Data available in Data Channel %d\n", i);
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/* if DMA is not enabled, field must be written with 1
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@ -566,17 +566,17 @@ static irqreturn_t micfil_isr(int irq, void *devid)
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if (!dma_enabled)
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regmap_write_bits(micfil->regmap,
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REG_MICFIL_STAT,
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MICFIL_STAT_CHXF_MASK(i),
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MICFIL_STAT_CHXF(i),
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1);
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}
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for (i = 0; i < MICFIL_FIFO_NUM; i++) {
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if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
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if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
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dev_dbg(&pdev->dev,
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"FIFO Overflow Exception flag for channel %d\n",
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i);
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if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
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if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
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dev_dbg(&pdev->dev,
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"FIFO Underflow Exception flag for channel %d\n",
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i);
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@ -39,82 +39,45 @@
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#define MICFIL_CTRL1_DBG BIT(28)
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#define MICFIL_CTRL1_SRES BIT(27)
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#define MICFIL_CTRL1_DBGE BIT(26)
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#define MICFIL_CTRL1_DISEL_SHIFT 24
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#define MICFIL_CTRL1_DISEL_WIDTH 2
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#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
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<< MICFIL_CTRL1_DISEL_SHIFT)
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#define MICFIL_CTRL1_DISEL_DISABLE 0
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#define MICFIL_CTRL1_DISEL_DMA 1
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#define MICFIL_CTRL1_DISEL_IRQ 2
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#define MICFIL_CTRL1_DISEL GENMASK(25, 24)
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#define MICFIL_CTRL1_ERREN BIT(23)
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#define MICFIL_CTRL1_CHEN_SHIFT 0
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#define MICFIL_CTRL1_CHEN_WIDTH 8
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#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
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#define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
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#define MICFIL_CTRL1_CHEN(ch) BIT(ch)
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/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
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#define MICFIL_CTRL2_QSEL_SHIFT 25
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#define MICFIL_CTRL2_QSEL_WIDTH 3
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#define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
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<< MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_CTRL2_QSEL GENMASK(27, 25)
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#define MICFIL_QSEL_MEDIUM_QUALITY 0
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#define MICFIL_QSEL_HIGH_QUALITY 1
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#define MICFIL_QSEL_LOW_QUALITY 7
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#define MICFIL_QSEL_VLOW0_QUALITY 6
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#define MICFIL_QSEL_VLOW1_QUALITY 5
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#define MICFIL_QSEL_VLOW2_QUALITY 4
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#define MICFIL_CTRL2_CICOSR_SHIFT 16
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#define MICFIL_CTRL2_CICOSR_WIDTH 4
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#define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
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<< MICFIL_CTRL2_CICOSR_SHIFT)
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#define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
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& MICFIL_CTRL2_CICOSR_MASK)
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#define MICFIL_CTRL2_CLKDIV_SHIFT 0
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#define MICFIL_CTRL2_CLKDIV_WIDTH 8
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#define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
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<< MICFIL_CTRL2_CLKDIV_SHIFT)
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#define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
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& MICFIL_CTRL2_CLKDIV_MASK)
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#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
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#define MICFIL_CTRL2_CICOSR_DEFAULT 0
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#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
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/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
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#define MICFIL_STAT_BSY_FIL BIT(31)
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#define MICFIL_STAT_FIR_RDY BIT(30)
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#define MICFIL_STAT_LOWFREQF BIT(29)
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#define MICFIL_STAT_CHXF_SHIFT(v) (v)
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#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
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#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
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#define MICFIL_STAT_CHXF(ch) BIT(ch)
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/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
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#define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0
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#define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
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#define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
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<< MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
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#define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
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& MICFIL_FIFO_CTRL_FIFOWMK_MASK)
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#define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
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/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
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#define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v)
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#define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
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#define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8)
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#define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
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#define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
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#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
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/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
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#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24
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#define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3
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#define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
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<< MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
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#define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
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& MICFIL_VAD0_CTRL1_CHSEL_MASK)
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#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16
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#define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4
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#define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
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<< MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
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#define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
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& MICFIL_VAD0_CTRL1_CICOSR_MASK)
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#define MICFIL_VAD0_CTRL1_INITT_SHIFT 8
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#define MICFIL_VAD0_CTRL1_INITT_WIDTH 5
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#define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
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<< MICFIL_VAD0_CTRL1_INITT_SHIFT)
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#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
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& MICFIL_VAD0_CTRL1_INITT_MASK)
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#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
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#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
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#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
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#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
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#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
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#define MICFIL_VAD0_CTRL1_IE BIT(2)
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@ -125,66 +88,26 @@
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#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
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#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
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#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
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#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
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#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
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#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
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<< MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
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#define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
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& MICFIL_VAD0_CTRL2_FRAMET_MASK)
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#define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
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#define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
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#define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
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<< MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
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#define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
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& MICFIL_VAD0_CTRL2_INPGAIN_MASK)
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#define MICFIL_VAD0_CTRL2_HPF_SHIFT 0
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#define MICFIL_VAD0_CTRL2_HPF_WIDTH 2
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#define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
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<< MICFIL_VAD0_CTRL2_HPF_SHIFT)
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#define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
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& MICFIL_VAD0_CTRL2_HPF_MASK)
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#define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
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#define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
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#define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
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/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
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#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
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#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
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#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
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#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
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#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
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<< MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
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#define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
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& MICFIL_VAD0_SCONFIG_SGAIN_MASK)
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#define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
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/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
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#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
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#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
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#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
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#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
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#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
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#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
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#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
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<< MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
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#define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
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& MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
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#define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0
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#define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4
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#define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
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<< MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
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#define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
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& MICFIL_VAD0_NCONFIG_NGAIN_MASK)
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#define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
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#define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
|
||||
|
||||
/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10
|
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#define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
|
||||
& MICFIL_VAD0_ZCD_ZCDTH_MASK)
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
|
||||
<< MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
|
||||
& MICFIL_VAD0_ZCD_ZCDADJ_MASK)
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
|
||||
#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
|
||||
@ -199,11 +122,6 @@
|
||||
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
|
||||
|
||||
/* Constants */
|
||||
#define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
|
||||
#define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
== ((v) & MICFIL_CTRL1_DISEL_MASK))
|
||||
#define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
== ((v) & MICFIL_CTRL1_DISEL_MASK))
|
||||
#define MICFIL_OUTPUT_CHANNELS 8
|
||||
#define MICFIL_FIFO_NUM 8
|
||||
|
||||
@ -215,6 +133,5 @@
|
||||
#define MICFIL_SLEEP_MIN 90000 /* in us */
|
||||
#define MICFIL_SLEEP_MAX 100000 /* in us */
|
||||
#define MICFIL_DMA_MAXBURST_RX 6
|
||||
#define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
|
||||
|
||||
#endif /* _FSL_MICFIL_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user