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drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:
commit 27c1cbd06a
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Apr 9 13:59:46 2012 +0100
drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
00c09d70df
commit
17f10fdc01
@ -1590,7 +1590,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
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ring->size = size;
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ring->effective_size = ring->size;
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if (IS_I830(ring->dev))
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if (IS_I830(ring->dev) || IS_845G(ring->dev))
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ring->effective_size -= 128;
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ring->virtual_start = ioremap_wc(start, size);
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