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ARM: at91: merge at91cap9_ddrsdr.h in at91sam9_ddrsdr.h
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Nicolas Ferre
parent
6522ecdcfa
commit
17d2cc25f0
@ -1,112 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
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*
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* (C) 2008 Andrew Victor
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*
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* DDR/SDR Controller (DDRSDRC) - System peripherals registers.
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* Based on AT91CAP9 datasheet revision B.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91CAP9_DDRSDR_H
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#define AT91CAP9_DDRSDR_H
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#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
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#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
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#define AT91_DDRSDRC_MODE_NORMAL 0
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#define AT91_DDRSDRC_MODE_NOP 1
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#define AT91_DDRSDRC_MODE_PRECHARGE 2
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#define AT91_DDRSDRC_MODE_LMR 3
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#define AT91_DDRSDRC_MODE_REFRESH 4
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#define AT91_DDRSDRC_MODE_EXT_LMR 5
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#define AT91_DDRSDRC_MODE_DEEP 6
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#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
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#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
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#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
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#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
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#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
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#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
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#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
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#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
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#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
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#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
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#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
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#define AT91_DDRSDRC_NR_11 (0 << 2)
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#define AT91_DDRSDRC_NR_12 (1 << 2)
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#define AT91_DDRSDRC_NR_13 (2 << 2)
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#define AT91_DDRSDRC_NR_14 (3 << 2)
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#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
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#define AT91_DDRSDRC_CAS_2 (2 << 4)
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#define AT91_DDRSDRC_CAS_3 (3 << 4)
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#define AT91_DDRSDRC_CAS_25 (6 << 4)
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#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
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#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
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#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
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#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
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#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
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#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
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#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
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#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
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#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
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#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
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#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
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#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
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#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
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#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
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#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_DDRSDRC_LPCB_DISABLE 0
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#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
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#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
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#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
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#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
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#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
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#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
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#define AT91_DDRSDRC_MD_SDR 0
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#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
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#define AT91_DDRSDRC_MD_DDR 2
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#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
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#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
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#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
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#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
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#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
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#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
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#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
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#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
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#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
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#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
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#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
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#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
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#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
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#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
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/* Register access macros */
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#define at91_ramc_read(num, reg) \
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at91_sys_read(AT91_DDRSDRC##num + reg)
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#define at91_ramc_write(num, reg, value) \
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at91_sys_write(AT91_DDRSDRC##num + reg, value)
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#endif
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@ -46,10 +46,10 @@
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#define AT91_DDRSDRC_CAS_25 (6 << 4)
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#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
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#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
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#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
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#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
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#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
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#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
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#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
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#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
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#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
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#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
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#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
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#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
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@ -59,7 +59,8 @@
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#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
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#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
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#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
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#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
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#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
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@ -68,13 +69,14 @@
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#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
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#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
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#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
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#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
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#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
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#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
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#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
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#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
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#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
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#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_DDRSDRC_LPCB_DISABLE 0
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#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
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@ -92,32 +94,40 @@
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#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
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#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
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#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
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#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
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#define AT91_DDRSDRC_MD_SDR 0
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#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
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#define AT91CAP9_DDRSDRC_MD_DDR 2
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#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
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#define AT91_DDRSDRC_MD_DDR2 6
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#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
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#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
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#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
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#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
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#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
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#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
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#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
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#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
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#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
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#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
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#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
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#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
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#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
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#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
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#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
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#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
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#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
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#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
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#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
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#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
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#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
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#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
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#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
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#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
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#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
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#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
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#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
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#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
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@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
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: : "r" (0))
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#elif defined(CONFIG_ARCH_AT91CAP9)
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#include <mach/at91cap9_ddrsdr.h>
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#include <mach/at91sam9_ddrsdr.h>
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
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lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
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at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
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#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
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#define wait_for_interrupt_enable() cpu_do_idle()
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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@ -18,9 +18,8 @@
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#if defined(CONFIG_ARCH_AT91RM9200)
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#include <mach/at91rm9200_mc.h>
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#elif defined(CONFIG_ARCH_AT91CAP9)
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#include <mach/at91cap9_ddrsdr.h>
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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#elif defined(CONFIG_ARCH_AT91CAP9) \
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|| defined(CONFIG_ARCH_AT91SAM9G45)
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#include <mach/at91sam9_ddrsdr.h>
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#else
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#include <mach/at91sam9_sdramc.h>
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