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perf vendor events: Update Intel broadwell
Update to v26, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwell files into perf and update mapfile.csv. Tested on a non-broadwell with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sedat Dilek <sedat.dilek@gmail.com> Cc: Stephane Eranian <eranian@google.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Link: http://lore.kernel.org/lkml/20220727220832.2865794-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
Arnaldo Carvalho de Melo
parent
4266081e33
commit
1775634ea4
@ -130,43 +130,25 @@
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"MetricName": "FLOPc_SMT"
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},
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{
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"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",
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"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
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"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
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"MetricGroup": "Cor;Flops;HPC",
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"MetricName": "FP_Arith_Utilization",
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"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."
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"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
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},
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{
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"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",
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"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). SMT version; use when SMT is enabled and measuring per logical CPU.",
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"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
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"MetricGroup": "Cor;Flops;HPC_SMT",
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"MetricName": "FP_Arith_Utilization_SMT",
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"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."
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"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common). SMT version; use when SMT is enabled and measuring per logical CPU."
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},
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{
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
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"MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
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"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
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"MetricName": "ILP"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts",
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"MetricName": "Branch_Misprediction_Cost"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts_SMT",
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"MetricName": "Branch_Misprediction_Cost_SMT"
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},
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{
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"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
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"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BadSpec;BrMispredicts",
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"MetricName": "IpMispredict"
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},
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{
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"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
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"MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
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@ -256,6 +238,18 @@
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"MetricGroup": "Summary;TmaL1",
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"MetricName": "Instructions"
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},
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{
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"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
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"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
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"MetricGroup": "Pipeline;Ret",
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"MetricName": "Retire"
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},
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{
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"BriefDescription": "",
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"MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
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"MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
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"MetricName": "Execute"
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},
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{
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"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
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"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
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@ -263,11 +257,28 @@
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"MetricName": "DSB_Coverage"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
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"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
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"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BadSpec;BrMispredicts",
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"MetricName": "IpMispredict"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts",
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"MetricName": "Branch_Misprediction_Cost"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts_SMT",
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"MetricName": "Branch_Misprediction_Cost_SMT"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
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"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
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"MetricGroup": "Mem;MemoryBound;MemoryLat",
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"MetricName": "Load_Miss_Real_Latency",
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"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
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"MetricName": "Load_Miss_Real_Latency"
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},
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{
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"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
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@ -275,24 +286,6 @@
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"MetricGroup": "Mem;MemoryBound;MemoryBW",
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"MetricName": "MLP"
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},
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{
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"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW"
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},
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{
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"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
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"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
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@ -306,13 +299,13 @@
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"MetricName": "L2MPKI"
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},
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{
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"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
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"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
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"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
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"MetricGroup": "Mem;CacheMisses;Offcore",
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"MetricName": "L2MPKI_All"
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},
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{
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"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)",
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"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
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"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
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"MetricGroup": "Mem;CacheMisses",
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"MetricName": "L2MPKI_Load"
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@ -348,6 +341,48 @@
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"MetricGroup": "Mem;MemoryTLB_SMT",
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"MetricName": "Page_Walks_Utilization_SMT"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "0",
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"MetricGroup": "Mem;MemoryBW;Offcore",
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"MetricName": "L3_Cache_Access_BW_1T"
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},
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{
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"BriefDescription": "Average CPU Utilization",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
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@ -364,7 +399,8 @@
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"BriefDescription": "Giga Floating Point Operations Per Second",
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"MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
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"MetricGroup": "Cor;Flops;HPC",
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"MetricName": "GFLOPs"
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"MetricName": "GFLOPs",
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"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
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},
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{
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"BriefDescription": "Average Frequency Utilization relative nominal frequency",
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@ -3407,4 +3407,4 @@
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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}
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]
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]
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@ -190,4 +190,4 @@
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"SampleAfterValue": "2000003",
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"UMask": "0x3"
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}
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]
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]
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@ -292,4 +292,4 @@
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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]
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@ -3050,4 +3050,4 @@
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"SampleAfterValue": "2000003",
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"UMask": "0x40"
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}
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]
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]
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@ -41,4 +41,4 @@
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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]
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@ -1377,4 +1377,4 @@
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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]
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152
tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
Normal file
152
tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
Normal file
@ -0,0 +1,152 @@
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[
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{
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"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
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"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
|
||||
"UMask": "0x86",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
|
||||
"UMask": "0x88",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
|
||||
"UMask": "0x81",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
|
||||
"UMask": "0x8f",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
|
||||
"UMask": "0x16",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
|
||||
"UMask": "0x18",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
|
||||
"UMask": "0x11",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
|
||||
"UMask": "0x1f",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
|
||||
"UMask": "0x26",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
|
||||
"UMask": "0x21",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
|
||||
"UMask": "0x2f",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x22",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
|
||||
"UMask": "0x48",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x22",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
|
||||
"UMask": "0x44",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x22",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
|
||||
"UMask": "0x81",
|
||||
"Unit": "CBO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x22",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
|
||||
"UMask": "0x41",
|
||||
"Unit": "CBO"
|
||||
}
|
||||
]
|
||||
82
tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
Normal file
82
tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
Normal file
@ -0,0 +1,82 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x84",
|
||||
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
|
||||
"Counter": "0,",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
|
||||
"Counter": "0,",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
|
||||
"Counter": "0,",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
|
||||
"UMask": "0x02",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x81",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x81",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
|
||||
"UMask": "0x02",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x81",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
|
||||
"UMask": "0x20",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
|
||||
"Counter": "FIXED",
|
||||
"EventCode": "0xff",
|
||||
"EventName": "UNC_CLOCK.SOCKET",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
|
||||
"Unit": "CLOCK"
|
||||
}
|
||||
]
|
||||
@ -1,278 +0,0 @@
|
||||
[
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x22",
|
||||
"UMask": "0x41",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
|
||||
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
|
||||
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x22",
|
||||
"UMask": "0x81",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
|
||||
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
|
||||
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x22",
|
||||
"UMask": "0x44",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
|
||||
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
|
||||
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x22",
|
||||
"UMask": "0x48",
|
||||
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
|
||||
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
|
||||
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x11",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x21",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
|
||||
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
|
||||
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x81",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x18",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x88",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x1f",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x2f",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
|
||||
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
|
||||
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x8f",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x86",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
|
||||
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
|
||||
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x16",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
|
||||
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
|
||||
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "CBO",
|
||||
"EventCode": "0x34",
|
||||
"UMask": "0x26",
|
||||
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
|
||||
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
|
||||
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x01",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
|
||||
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
|
||||
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
|
||||
"Counter": "0,",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x02",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
|
||||
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
|
||||
"PublicDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
|
||||
"Counter": "0,",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x81",
|
||||
"UMask": "0x01",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
|
||||
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
|
||||
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x81",
|
||||
"UMask": "0x02",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
|
||||
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
|
||||
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x81",
|
||||
"UMask": "0x20",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
|
||||
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
|
||||
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x84",
|
||||
"UMask": "0x01",
|
||||
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
|
||||
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
|
||||
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "iMPH-U",
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x01",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
|
||||
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
|
||||
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
|
||||
"Counter": "0,",
|
||||
"CounterMask": "1",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
},
|
||||
{
|
||||
"Unit": "NCU",
|
||||
"EventCode": "0x0",
|
||||
"UMask": "0x01",
|
||||
"EventName": "UNC_CLOCK.SOCKET",
|
||||
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
|
||||
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
|
||||
"Counter": "FIXED",
|
||||
"CounterMask": "0",
|
||||
"Invert": "0",
|
||||
"EdgeDetect": "0"
|
||||
}
|
||||
]
|
||||
@ -385,4 +385,4 @@
|
||||
"SampleAfterValue": "100007",
|
||||
"UMask": "0x20"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
1246
tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
Normal file
1246
tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,6 @@
|
||||
Family-model,Version,Filename,EventType
|
||||
GenuineIntel-6-56,v5,broadwellde,core
|
||||
GenuineIntel-6-3D,v17,broadwell,core
|
||||
GenuineIntel-6-47,v17,broadwell,core
|
||||
GenuineIntel-6-(3D|47),v26,broadwell,core
|
||||
GenuineIntel-6-4F,v19,broadwellx,core
|
||||
GenuineIntel-6-1C,v4,bonnell,core
|
||||
GenuineIntel-6-26,v4,bonnell,core
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user