ARM: 5650/1: bcmring: add io.h, uncompress. h, and entry-macro.S

add remaining header files in include/mach directory
add entry-macro.S file

Signed-off-by: Leo Chen <leochen@broadcom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Leo Chen 2009-08-07 20:02:21 +01:00 committed by Russell King
parent 3455912574
commit 16f5875034
3 changed files with 185 additions and 0 deletions

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/*****************************************************************************
* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/*
*
* Low-level IRQ helper macros for BCMRing-based platforms
*
*/
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(MM_IO_BASE_INTC0)
ldr \irqstat, [\base, #0] @ get status
ldr \irqnr, [\base, #0x10] @ mask with enable register
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #IRQ_INTC0_START
cmp \irqstat, #0
bne 1001f
ldr \base, =(MM_IO_BASE_INTC1)
ldr \irqstat, [\base, #0] @ get status
ldr \irqnr, [\base, #0x10] @ mask with enable register
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #IRQ_INTC1_START
cmp \irqstat, #0
bne 1001f
ldr \base, =(MM_IO_BASE_SINTC)
ldr \irqstat, [\base, #0] @ get status
ldr \irqnr, [\base, #0x10] @ mask with enable register
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
cmp \irqstat, #0
beq 1002f
mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
1001:
movs \tmp, \irqstat, lsl #16
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #16
movs \tmp, \irqstat, lsl #8
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #8
movs \tmp, \irqstat, lsl #4
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #4
movs \tmp, \irqstat, lsl #2
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #2
movs \tmp, \irqstat, lsl #1
addeq \irqnr, \irqnr, #1
orrs \base, \base, #1
1002: @ irqnr will be set to 0xffffffff if no irq bits are set
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro irq_prio_table
.endm

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/*
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)HW_IO_PHYS_TO_VIRT(a))
/* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */
/* happen in readw/writew etc. */
#define readb(c) __raw_readb(c)
#define readw(c) __raw_readw(c)
#define readl(c) __raw_readl(c)
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define readsb(p, d, l) __raw_readsb(p, d, l)
#define readsw(p, d, l) __raw_readsw(p, d, l)
#define readsl(p, d, l) __raw_readsl(p, d, l)
#define writeb(v, c) __raw_writeb(v, c)
#define writew(v, c) __raw_writew(v, c)
#define writel(v, c) __raw_writel(v, c)
#define writesb(p, d, l) __raw_writesb(p, d, l)
#define writesw(p, d, l) __raw_writesw(p, d, l)
#define writesl(p, d, l) __raw_writesl(p, d, l)
#define memset_io(c, v, l) _memset_io((c), (v), (l))
#define memcpy_fromio(a, c, l) _memcpy_fromio((a), (c), (l))
#define memcpy_toio(c, a, l) _memcpy_toio((c), (a), (l))
#define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b))
#endif

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/*****************************************************************************
* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <mach/csp/mm_addr.h>
#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
/*
* This does not append a newline
*/
static inline void putc(int c)
{
/* Send out UARTA */
while (BCMRING_UART_0_FR & (1 << 5))
;
BCMRING_UART_0_DR = c;
}
static inline void flush(void)
{
/* Wait for the tx fifo to be empty */
while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
;
/* Wait for the final character to be sent on the txd line */
while (BCMRING_UART_0_FR & (1 << 3))
;
}
#define arch_decomp_setup()
#define arch_decomp_wdog()