Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-11 05:33:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branches 'acpi-processor', 'acpi-cppc' and 'acpi-pmic'

Browse Source 
* acpi-processor:
  ACPI / Processor: Drop setup_max_cpus check from acpi_processor_add()

* acpi-cppc:
  ACPI / CPPC: add sysfs entries for CPPC perf capabilities
  ACPI / CPPC: Read lowest nonlinear perf in cppc_get_perf_caps()

* acpi-pmic:
  ACPI / PMIC: Stop xpower OPRegion handler relying on IIO
  ACPI / PMIC: Add opregion driver for Intel CHT Whiskey Cove PMIC
This commit is contained in:
Rafael J. Wysocki 2017-04-28 23:17:55 +02:00
commit 168f4a6950
7 changed files with 338 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/acpi/Kconfig
View File

@ -506,7 +506,7 @@ config CRC_PMIC_OPREGION
config XPOWER_PMIC_OPREGION
bool "ACPI operation region support for XPower AXP288 PMIC"
depends on AXP288_ADC = y
depends on MFD_AXP20X_I2C
help
This config adds ACPI operation region support for XPower AXP288 PMIC.
@ -516,6 +516,12 @@ config BXT_WC_PMIC_OPREGION
help
This config adds ACPI operation region support for BXT WhiskeyCove PMIC.
config CHT_WC_PMIC_OPREGION
bool "ACPI operation region support for CHT Whiskey Cove PMIC"
depends on INTEL_SOC_PMIC_CHTWC
help
This config adds ACPI operation region support for CHT Whiskey Cove PMIC.
endif
config ACPI_CONFIGFS

1
drivers/acpi/Makefile
View File

@ -101,6 +101,7 @@ obj-$(CONFIG_PMIC_OPREGION) += pmic/intel_pmic.o
obj-$(CONFIG_CRC_PMIC_OPREGION) += pmic/intel_pmic_crc.o
obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
obj-$(CONFIG_ACPI_CONFIGFS) += acpi_configfs.o

5
drivers/acpi/acpi_processor.c
View File

@ -388,11 +388,6 @@ static int acpi_processor_add(struct acpi_device *device,
if (result) /* Processor is not physically present or unavailable */
return 0;
#ifdef CONFIG_SMP
if (pr->id >= setup_max_cpus && pr->id != 0)
return 0;
#endif
BUG_ON(pr->id >= nr_cpu_ids);
/*

80
drivers/acpi/cppc_acpi.c
View File

@ -132,49 +132,54 @@ __ATTR(_name, 0444, show_##_name, NULL)
#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
#define show_cppc_data(access_fn, struct_name, member_name) \
static ssize_t show_##member_name(struct kobject *kobj, \
struct attribute *attr, char *buf) \
{ \
struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
struct struct_name st_name = {0}; \
int ret; \
\
ret = access_fn(cpc_ptr->cpu_id, &st_name); \
if (ret) \
return ret; \
\
return scnprintf(buf, PAGE_SIZE, "%llu\n", \
(u64)st_name.member_name); \
} \
define_one_cppc_ro(member_name)
show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
static ssize_t show_feedback_ctrs(struct kobject *kobj,
struct attribute *attr, char *buf)
{
struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
struct cppc_perf_fb_ctrs fb_ctrs = {0};
int ret;
cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
if (ret)
return ret;
return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
fb_ctrs.reference, fb_ctrs.delivered);
}
define_one_cppc_ro(feedback_ctrs);
static ssize_t show_reference_perf(struct kobject *kobj,
struct attribute *attr, char *buf)
{
struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
struct cppc_perf_fb_ctrs fb_ctrs = {0};
cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
return scnprintf(buf, PAGE_SIZE, "%llu\n",
fb_ctrs.reference_perf);
}
define_one_cppc_ro(reference_perf);
static ssize_t show_wraparound_time(struct kobject *kobj,
struct attribute *attr, char *buf)
{
struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
struct cppc_perf_fb_ctrs fb_ctrs = {0};
cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
return scnprintf(buf, PAGE_SIZE, "%llu\n", fb_ctrs.ctr_wrap_time);
}
define_one_cppc_ro(wraparound_time);
static struct attribute *cppc_attrs[] = {
&feedback_ctrs.attr,
&reference_perf.attr,
&wraparound_time.attr,
&highest_perf.attr,
&lowest_perf.attr,
&lowest_nonlinear_perf.attr,
&nominal_perf.attr,
NULL
};
@ -972,9 +977,9 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
{
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf,
*nom_perf;
u64 high, low, nom;
struct cpc_register_resource *highest_reg, *lowest_reg,
*lowest_non_linear_reg, *nominal_reg;
u64 high, low, nom, min_nonlinear;
int ret = 0, regs_in_pcc = 0;
if (!cpc_desc) {
@ -984,12 +989,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF];
nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF];
lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
/* Are any of the regs PCC ?*/
if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
CPC_IN_PCC(ref_perf) || CPC_IN_PCC(nom_perf)) {
CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg)) {
regs_in_pcc = 1;
down_write(&pcc_data.pcc_lock);
/* Ring doorbell once to update PCC subspace */
@ -1005,10 +1010,13 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
cpc_read(cpunum, lowest_reg, &low);
perf_caps->lowest_perf = low;
cpc_read(cpunum, nom_perf, &nom);
cpc_read(cpunum, nominal_reg, &nom);
perf_caps->nominal_perf = nom;
if (!high || !low || !nom)
cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
perf_caps->lowest_nonlinear_perf = min_nonlinear;
if (!high || !low || !nom || !min_nonlinear)
ret = -EFAULT;
out_err:
@ -1083,7 +1091,7 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
perf_fb_ctrs->delivered = delivered;
perf_fb_ctrs->reference = reference;
perf_fb_ctrs->reference_perf = ref_perf;
perf_fb_ctrs->ctr_wrap_time = ctr_wrap_time;
perf_fb_ctrs->wraparound_time = ctr_wrap_time;
out_err:
if (regs_in_pcc)
up_write(&pcc_data.pcc_lock);

280
drivers/acpi/pmic/intel_pmic_chtwc.c Normal file
View File

@ -0,0 +1,280 @@
/*
* Intel CHT Whiskey Cove PMIC operation region driver
* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
*
* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "intel_pmic.h"
#define CHT_WC_V1P05A_CTRL 0x6e3b
#define CHT_WC_V1P15_CTRL 0x6e3c
#define CHT_WC_V1P05A_VSEL 0x6e3d
#define CHT_WC_V1P15_VSEL 0x6e3e
#define CHT_WC_V1P8A_CTRL 0x6e56
#define CHT_WC_V1P8SX_CTRL 0x6e57
#define CHT_WC_VDDQ_CTRL 0x6e58
#define CHT_WC_V1P2A_CTRL 0x6e59
#define CHT_WC_V1P2SX_CTRL 0x6e5a
#define CHT_WC_V1P8A_VSEL 0x6e5b
#define CHT_WC_VDDQ_VSEL 0x6e5c
#define CHT_WC_V2P8SX_CTRL 0x6e5d
#define CHT_WC_V3P3A_CTRL 0x6e5e
#define CHT_WC_V3P3SD_CTRL 0x6e5f
#define CHT_WC_VSDIO_CTRL 0x6e67
#define CHT_WC_V3P3A_VSEL 0x6e68
#define CHT_WC_VPROG1A_CTRL 0x6e90
#define CHT_WC_VPROG1B_CTRL 0x6e91
#define CHT_WC_VPROG1F_CTRL 0x6e95
#define CHT_WC_VPROG2D_CTRL 0x6e99
#define CHT_WC_VPROG3A_CTRL 0x6e9a
#define CHT_WC_VPROG3B_CTRL 0x6e9b
#define CHT_WC_VPROG4A_CTRL 0x6e9c
#define CHT_WC_VPROG4B_CTRL 0x6e9d
#define CHT_WC_VPROG4C_CTRL 0x6e9e
#define CHT_WC_VPROG4D_CTRL 0x6e9f
#define CHT_WC_VPROG5A_CTRL 0x6ea0
#define CHT_WC_VPROG5B_CTRL 0x6ea1
#define CHT_WC_VPROG6A_CTRL 0x6ea2
#define CHT_WC_VPROG6B_CTRL 0x6ea3
#define CHT_WC_VPROG1A_VSEL 0x6ec0
#define CHT_WC_VPROG1B_VSEL 0x6ec1
#define CHT_WC_V1P8SX_VSEL 0x6ec2
#define CHT_WC_V1P2SX_VSEL 0x6ec3
#define CHT_WC_V1P2A_VSEL 0x6ec4
#define CHT_WC_VPROG1F_VSEL 0x6ec5
#define CHT_WC_VSDIO_VSEL 0x6ec6
#define CHT_WC_V2P8SX_VSEL 0x6ec7
#define CHT_WC_V3P3SD_VSEL 0x6ec8
#define CHT_WC_VPROG2D_VSEL 0x6ec9
#define CHT_WC_VPROG3A_VSEL 0x6eca
#define CHT_WC_VPROG3B_VSEL 0x6ecb
#define CHT_WC_VPROG4A_VSEL 0x6ecc
#define CHT_WC_VPROG4B_VSEL 0x6ecd
#define CHT_WC_VPROG4C_VSEL 0x6ece
#define CHT_WC_VPROG4D_VSEL 0x6ecf
#define CHT_WC_VPROG5A_VSEL 0x6ed0
#define CHT_WC_VPROG5B_VSEL 0x6ed1
#define CHT_WC_VPROG6A_VSEL 0x6ed2
#define CHT_WC_VPROG6B_VSEL 0x6ed3
/*
* Regulator support is based on the non upstream patch:
* "regulator: whiskey_cove: implements Whiskey Cove pmic VRF support"
* https://github.com/intel-aero/meta-intel-aero/blob/master/recipes-kernel/linux/linux-yocto/0019-regulator-whiskey_cove-implements-WhiskeyCove-pmic-V.patch
*/
static struct pmic_table power_table[] = {
{
.address = 0x0,
.reg = CHT_WC_V1P8A_CTRL,
.bit = 0x01,
}, /* V18A */
{
.address = 0x04,
.reg = CHT_WC_V1P8SX_CTRL,
.bit = 0x07,
}, /* V18X */
{
.address = 0x08,
.reg = CHT_WC_VDDQ_CTRL,
.bit = 0x01,
}, /* VDDQ */
{
.address = 0x0c,
.reg = CHT_WC_V1P2A_CTRL,
.bit = 0x07,
}, /* V12A */
{
.address = 0x10,
.reg = CHT_WC_V1P2SX_CTRL,
.bit = 0x07,
}, /* V12X */
{
.address = 0x14,
.reg = CHT_WC_V2P8SX_CTRL,
.bit = 0x07,
}, /* V28X */
{
.address = 0x18,
.reg = CHT_WC_V3P3A_CTRL,
.bit = 0x01,
}, /* V33A */
{
.address = 0x1c,
.reg = CHT_WC_V3P3SD_CTRL,
.bit = 0x07,
}, /* V3SD */
{
.address = 0x20,
.reg = CHT_WC_VSDIO_CTRL,
.bit = 0x07,
}, /* VSD */
/* {
.address = 0x24,
.reg = ??,
.bit = ??,
}, ** VSW2 */
/* {
.address = 0x28,
.reg = ??,
.bit = ??,
}, ** VSW1 */
/* {
.address = 0x2c,
.reg = ??,
.bit = ??,
}, ** VUPY */
/* {
.address = 0x30,
.reg = ??,
.bit = ??,
}, ** VRSO */
{
.address = 0x34,
.reg = CHT_WC_VPROG1A_CTRL,
.bit = 0x07,
}, /* VP1A */
{
.address = 0x38,
.reg = CHT_WC_VPROG1B_CTRL,
.bit = 0x07,
}, /* VP1B */
{
.address = 0x3c,
.reg = CHT_WC_VPROG1F_CTRL,
.bit = 0x07,
}, /* VP1F */
{
.address = 0x40,
.reg = CHT_WC_VPROG2D_CTRL,
.bit = 0x07,
}, /* VP2D */
{
.address = 0x44,
.reg = CHT_WC_VPROG3A_CTRL,
.bit = 0x07,
}, /* VP3A */
{
.address = 0x48,
.reg = CHT_WC_VPROG3B_CTRL,
.bit = 0x07,
}, /* VP3B */
{
.address = 0x4c,
.reg = CHT_WC_VPROG4A_CTRL,
.bit = 0x07,
}, /* VP4A */
{
.address = 0x50,
.reg = CHT_WC_VPROG4B_CTRL,
.bit = 0x07,
}, /* VP4B */
{
.address = 0x54,
.reg = CHT_WC_VPROG4C_CTRL,
.bit = 0x07,
}, /* VP4C */
{
.address = 0x58,
.reg = CHT_WC_VPROG4D_CTRL,
.bit = 0x07,
}, /* VP4D */
{
.address = 0x5c,
.reg = CHT_WC_VPROG5A_CTRL,
.bit = 0x07,
}, /* VP5A */
{
.address = 0x60,
.reg = CHT_WC_VPROG5B_CTRL,
.bit = 0x07,
}, /* VP5B */
{
.address = 0x64,
.reg = CHT_WC_VPROG6A_CTRL,
.bit = 0x07,
}, /* VP6A */
{
.address = 0x68,
.reg = CHT_WC_VPROG6B_CTRL,
.bit = 0x07,
}, /* VP6B */
/* {
.address = 0x6c,
.reg = ??,
.bit = ??,
} ** VP7A */
};
static int intel_cht_wc_pmic_get_power(struct regmap *regmap, int reg,
int bit, u64 *value)
{
int data;
if (regmap_read(regmap, reg, &data))
return -EIO;
*value = (data & bit) ? 1 : 0;
return 0;
}
static int intel_cht_wc_pmic_update_power(struct regmap *regmap, int reg,
int bitmask, bool on)
{
return regmap_update_bits(regmap, reg, bitmask, on ? 1 : 0);
}
/*
* The thermal table and ops are empty, we do not support the Thermal opregion
* (DPTF) due to lacking documentation.
*/
static struct intel_pmic_opregion_data intel_cht_wc_pmic_opregion_data = {
.get_power = intel_cht_wc_pmic_get_power,
.update_power = intel_cht_wc_pmic_update_power,
.power_table = power_table,
.power_table_count = ARRAY_SIZE(power_table),
};
static int intel_cht_wc_pmic_opregion_probe(struct platform_device *pdev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
return intel_pmic_install_opregion_handler(&pdev->dev,
ACPI_HANDLE(pdev->dev.parent),
pmic->regmap,
&intel_cht_wc_pmic_opregion_data);
}
static struct platform_device_id cht_wc_opregion_id_table[] = {
{ .name = "cht_wcove_region" },
{},
};
MODULE_DEVICE_TABLE(platform, cht_wc_opregion_id_table);
static struct platform_driver intel_cht_wc_pmic_opregion_driver = {
.probe = intel_cht_wc_pmic_opregion_probe,
.driver = {
.name = "cht_whiskey_cove_pmic",
},
.id_table = cht_wc_opregion_id_table,
};
module_platform_driver(intel_cht_wc_pmic_opregion_driver);
MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC operation region driver");
MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
MODULE_LICENSE("GPL");

21
drivers/acpi/pmic/intel_pmic_xpower.c
View File

@ -18,7 +18,6 @@
#include <linux/mfd/axp20x.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/iio/consumer.h>
#include "intel_pmic.h"
#define XPOWER_GPADC_LOW 0x5b
@ -186,28 +185,16 @@ static int intel_xpower_pmic_update_power(struct regmap *regmap, int reg,
* @regmap: regmap of the PMIC device
* @reg: register to get the reading
*
* We could get the sensor value by manipulating the HW regs here, but since
* the axp288 IIO driver may also access the same regs at the same time, the
* APIs provided by IIO subsystem are used here instead to avoid problems. As
* a result, the two passed in params are of no actual use.
*
* Return a positive value on success, errno on failure.
*/
static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)
{
struct iio_channel *gpadc_chan;
int ret, val;
u8 buf[2];
gpadc_chan = iio_channel_get(NULL, "axp288-system-temp");
if (IS_ERR_OR_NULL(gpadc_chan))
return -EACCES;
if (regmap_bulk_read(regmap, AXP288_GP_ADC_H, buf, 2))
return -EIO;
ret = iio_read_channel_raw(gpadc_chan, &val);
if (ret < 0)
val = ret;
iio_channel_release(gpadc_chan);
return val;
return (buf[0] << 4) + ((buf[1] >> 4) & 0x0F);
}
static struct intel_pmic_opregion_data intel_xpower_pmic_opregion_data = {

3
include/acpi/cppc_acpi.h
View File

@ -103,6 +103,7 @@ struct cppc_perf_caps {
u32 highest_perf;
u32 nominal_perf;
u32 lowest_perf;
u32 lowest_nonlinear_perf;
};
struct cppc_perf_ctrls {
@ -115,7 +116,7 @@ struct cppc_perf_fb_ctrs {
u64 reference;
u64 delivered;
u64 reference_perf;
u64 ctr_wrap_time;
u64 wraparound_time;
};
/* Per CPU container for runtime CPPC management. */