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drm/amdgpu/vcn: update vcn4 fw shared data structure
update VF_RB_SETUP_FLAG, add SMU_DPM_INTERFACE_FLAG, and corresponding change in VCN4. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -161,7 +161,8 @@
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#define AMDGPU_VCN_SW_RING_FLAG (1 << 9)
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#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
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#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
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#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 12)
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#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
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#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
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#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
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#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
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@ -171,6 +172,9 @@
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#define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2)
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#define VCN_CODEC_DISABLE_MASK_H264 (1 << 3)
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#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0)
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#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1)
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enum fw_queue_mode {
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FW_QUEUE_RING_RESET = 1,
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FW_QUEUE_DPG_HOLD_OFF = 2,
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@ -335,7 +339,9 @@ struct amdgpu_vcn4_fw_shared {
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struct amdgpu_fw_shared_unified_queue_struct sq;
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uint8_t pad1[8];
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struct amdgpu_fw_shared_fw_logging fw_log;
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uint8_t pad2[20];
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struct amdgpu_fw_shared_rb_setup rb_setup;
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struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
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};
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struct amdgpu_vcn_fwlog {
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@ -150,6 +150,10 @@ static int vcn_v4_0_sw_init(void *handle)
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fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
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fw_shared->sq.is_enabled = 1;
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fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
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fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
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AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
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if (amdgpu_sriov_vf(adev))
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fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
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