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pinctrl: renesas: r8a779h0: Add PCIe pins, groups, functions

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Add pins, groups and functions for the PCIe Controller on the Renesas
R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d32909f5197fa2df0ca6bd6e5fda7cae8863101e.1706264667.git.geert+renesas@glider.be
This commit is contained in:
Cong Dang 2024-01-26 11:44:11 +01:00 committed by Geert Uytterhoeven
parent 2acf13cec9
commit 1604b9788e
1 changed files with 18 additions and 0 deletions
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18
drivers/pinctrl/renesas/pfc-r8a779h0.c
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@ -1951,6 +1951,16 @@ static const unsigned int msiof5_rxd_mux[] = {
MSIOF5_RXD_MARK,
};
/* - PCIE ------------------------------------------------------------------- */
static const unsigned int pcie0_clkreq_n_pins[] = {
/* PCIE0_CLKREQ_N */
RCAR_GP_PIN(4, 21),
};
static const unsigned int pcie0_clkreq_n_mux[] = {
PCIE0_CLKREQ_N_MARK,
};
/* - PWM0_A ------------------------------------------------------------------- */
static const unsigned int pwm0_a_pins[] = {
/* PWM0_A */
@ -2421,6 +2431,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof5_txd),
SH_PFC_PIN_GROUP(msiof5_rxd),
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pwm0_a),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm1_a),
@ -2638,6 +2650,10 @@ static const char * const msiof5_groups[] = {
"msiof5_rxd",
};
static const char * const pcie_groups[] = {
"pcie0_clkreq_n",
};
static const char * const pwm0_groups[] = {
"pwm0_a",
"pwm0_b",
@ -2756,6 +2772,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof4),
SH_PFC_FUNCTION(msiof5),
SH_PFC_FUNCTION(pcie),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),