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ath9k_hw: Implement AR9003 eeprom callbacks
Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Senthil Balasubramanian
John W. Linville
parent
49101676b2
commit
15c9ee7af8
@ -30,7 +30,8 @@ ath9k_hw-y:= \
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ani.o \
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btcoex.o \
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mac.o \
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ar9003_mac.o
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ar9003_mac.o \
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ar9003_eeprom.o
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obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
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1842
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
Normal file
1842
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
Normal file
File diff suppressed because it is too large
Load Diff
319
drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
Normal file
319
drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
Normal file
@ -0,0 +1,319 @@
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#ifndef AR9003_EEPROM_H
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#define AR9003_EEPROM_H
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#include <linux/types.h>
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#define AR9300_EEP_VER 0xD000
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#define AR9300_EEP_VER_MINOR_MASK 0xFFF
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#define AR9300_EEP_MINOR_VER_1 0x1
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#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
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/* 16-bit offset location start of calibration struct */
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#define AR9300_EEP_START_LOC 256
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#define AR9300_NUM_5G_CAL_PIERS 8
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#define AR9300_NUM_2G_CAL_PIERS 3
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#define AR9300_NUM_5G_20_TARGET_POWERS 8
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#define AR9300_NUM_5G_40_TARGET_POWERS 8
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#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
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#define AR9300_NUM_2G_20_TARGET_POWERS 3
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#define AR9300_NUM_2G_40_TARGET_POWERS 3
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/* #define AR9300_NUM_CTLS 21 */
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#define AR9300_NUM_CTLS_5G 9
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#define AR9300_NUM_CTLS_2G 12
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#define AR9300_CTL_MODE_M 0xF
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#define AR9300_NUM_BAND_EDGES_5G 8
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#define AR9300_NUM_BAND_EDGES_2G 4
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#define AR9300_NUM_PD_GAINS 4
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#define AR9300_PD_GAINS_IN_MASK 4
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#define AR9300_PD_GAIN_ICEPTS 5
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#define AR9300_EEPROM_MODAL_SPURS 5
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#define AR9300_MAX_RATE_POWER 63
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#define AR9300_NUM_PDADC_VALUES 128
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#define AR9300_NUM_RATES 16
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#define AR9300_BCHAN_UNUSED 0xFF
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#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
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#define AR9300_OPFLAGS_11A 0x01
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#define AR9300_OPFLAGS_11G 0x02
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#define AR9300_OPFLAGS_5G_HT40 0x04
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#define AR9300_OPFLAGS_2G_HT40 0x08
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#define AR9300_OPFLAGS_5G_HT20 0x10
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#define AR9300_OPFLAGS_2G_HT20 0x20
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#define AR9300_EEPMISC_BIG_ENDIAN 0x01
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#define AR9300_EEPMISC_WOW 0x02
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#define AR9300_CUSTOMER_DATA_SIZE 20
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#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
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#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
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#define AR9300_MAX_CHAINS 3
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#define AR9300_ANT_16S 25
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#define AR9300_FUTURE_MODAL_SZ 6
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#define AR9300_NUM_ANT_CHAIN_FIELDS 7
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#define AR9300_NUM_ANT_COMMON_FIELDS 4
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#define AR9300_SIZE_ANT_CHAIN_FIELD 3
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#define AR9300_SIZE_ANT_COMMON_FIELD 4
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#define AR9300_ANT_CHAIN_MASK 0x7
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#define AR9300_ANT_COMMON_MASK 0xf
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#define AR9300_CHAIN_0_IDX 0
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#define AR9300_CHAIN_1_IDX 1
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#define AR9300_CHAIN_2_IDX 2
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#define AR928X_NUM_ANT_CHAIN_FIELDS 6
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#define AR928X_SIZE_ANT_CHAIN_FIELD 2
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#define AR928X_ANT_CHAIN_MASK 0x3
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/* Delta from which to start power to pdadc table */
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/* This offset is used in both open loop and closed loop power control
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* schemes. In open loop power control, it is not really needed, but for
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* the "sake of consistency" it was kept. For certain AP designs, this
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* value is overwritten by the value in the flag "pwrTableOffset" just
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* before writing the pdadc vs pwr into the chip registers.
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*/
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#define AR9300_PWR_TABLE_OFFSET 0
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/* enable flags for voltage and temp compensation */
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#define ENABLE_TEMP_COMPENSATION 0x01
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#define ENABLE_VOLT_COMPENSATION 0x02
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/* byte addressable */
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#define AR9300_EEPROM_SIZE (16*1024)
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#define FIXED_CCA_THRESHOLD 15
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#define AR9300_BASE_ADDR 0x3ff
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enum targetPowerHTRates {
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HT_TARGET_RATE_0_8_16,
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HT_TARGET_RATE_1_3_9_11_17_19,
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HT_TARGET_RATE_4,
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HT_TARGET_RATE_5,
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HT_TARGET_RATE_6,
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HT_TARGET_RATE_7,
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HT_TARGET_RATE_12,
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HT_TARGET_RATE_13,
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HT_TARGET_RATE_14,
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HT_TARGET_RATE_15,
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HT_TARGET_RATE_20,
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HT_TARGET_RATE_21,
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HT_TARGET_RATE_22,
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HT_TARGET_RATE_23
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};
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enum targetPowerLegacyRates {
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LEGACY_TARGET_RATE_6_24,
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LEGACY_TARGET_RATE_36,
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LEGACY_TARGET_RATE_48,
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LEGACY_TARGET_RATE_54
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};
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enum targetPowerCckRates {
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LEGACY_TARGET_RATE_1L_5L,
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LEGACY_TARGET_RATE_5S,
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LEGACY_TARGET_RATE_11L,
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LEGACY_TARGET_RATE_11S
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};
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enum ar9300_Rates {
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_36,
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ALL_TARGET_LEGACY_48,
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ALL_TARGET_LEGACY_54,
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ALL_TARGET_LEGACY_1L_5L,
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ALL_TARGET_LEGACY_5S,
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ALL_TARGET_LEGACY_11L,
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ALL_TARGET_LEGACY_11S,
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ALL_TARGET_HT20_0_8_16,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_4,
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ALL_TARGET_HT20_5,
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ALL_TARGET_HT20_6,
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ALL_TARGET_HT20_7,
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ALL_TARGET_HT20_12,
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ALL_TARGET_HT20_13,
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ALL_TARGET_HT20_14,
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ALL_TARGET_HT20_15,
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ALL_TARGET_HT20_20,
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ALL_TARGET_HT20_21,
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ALL_TARGET_HT20_22,
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ALL_TARGET_HT20_23,
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ALL_TARGET_HT40_0_8_16,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_4,
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ALL_TARGET_HT40_5,
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ALL_TARGET_HT40_6,
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ALL_TARGET_HT40_7,
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ALL_TARGET_HT40_12,
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ALL_TARGET_HT40_13,
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ALL_TARGET_HT40_14,
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ALL_TARGET_HT40_15,
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ALL_TARGET_HT40_20,
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ALL_TARGET_HT40_21,
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ALL_TARGET_HT40_22,
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ALL_TARGET_HT40_23,
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ar9300RateSize,
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};
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struct eepFlags {
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u8 opFlags;
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u8 eepMisc;
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} __packed;
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enum CompressAlgorithm {
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_CompressNone = 0,
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_CompressLzma,
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_CompressPairs,
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_CompressBlock,
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_Compress4,
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_Compress5,
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_Compress6,
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_Compress7,
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};
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struct ar9300_base_eep_hdr {
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u16 regDmn[2];
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/* 4 bits tx and 4 bits rx */
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u8 txrxMask;
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struct eepFlags opCapFlags;
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u8 rfSilent;
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u8 blueToothOptions;
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u8 deviceCap;
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/* takes lower byte in eeprom location */
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u8 deviceType;
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/* offset in dB to be added to beginning
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* of pdadc table in calibration
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*/
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int8_t pwrTableOffset;
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u8 params_for_tuning_caps[2];
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/*
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* bit0 - enable tx temp comp
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* bit1 - enable tx volt comp
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* bit2 - enable fastClock - default to 1
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* bit3 - enable doubling - default to 1
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* bit4 - enable internal regulator - default to 1
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*/
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u8 featureEnable;
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/* misc flags: bit0 - turn down drivestrength */
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u8 miscConfiguration;
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u8 eepromWriteEnableGpio;
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u8 wlanDisableGpio;
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u8 wlanLedGpio;
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u8 rxBandSelectGpio;
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u8 txrxgain;
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/* SW controlled internal regulator fields */
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u32 swreg;
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} __packed;
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struct ar9300_modal_eep_header {
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/* 4 idle, t1, t2, b (4 bits per setting) */
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u32 antCtrlCommon;
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/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
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u32 antCtrlCommon2;
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/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
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u16 antCtrlChain[AR9300_MAX_CHAINS];
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/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
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u8 xatten1DB[AR9300_MAX_CHAINS];
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/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
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u8 xatten1Margin[AR9300_MAX_CHAINS];
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int8_t tempSlope;
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int8_t voltSlope;
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/* spur channels in usual fbin coding format */
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u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
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/* 3 Check if the register is per chain */
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int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
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u8 ob[AR9300_MAX_CHAINS];
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u8 db_stage2[AR9300_MAX_CHAINS];
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u8 db_stage3[AR9300_MAX_CHAINS];
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u8 db_stage4[AR9300_MAX_CHAINS];
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u8 xpaBiasLvl;
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u8 txFrameToDataStart;
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u8 txFrameToPaOn;
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u8 txClip;
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int8_t antennaGain;
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u8 switchSettling;
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int8_t adcDesiredSize;
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u8 txEndToXpaOff;
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u8 txEndToRxOn;
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u8 txFrameToXpaOn;
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u8 thresh62;
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u8 futureModal[32];
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} __packed;
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struct ar9300_cal_data_per_freq_op_loop {
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int8_t refPower;
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/* pdadc voltage at power measurement */
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u8 voltMeas;
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/* pcdac used for power measurement */
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u8 tempMeas;
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/* range is -60 to -127 create a mapping equation 1db resolution */
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int8_t rxNoisefloorCal;
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/*range is same as noisefloor */
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int8_t rxNoisefloorPower;
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/* temp measured when noisefloor cal was performed */
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u8 rxTempMeas;
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} __packed;
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struct cal_tgt_pow_legacy {
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u8 tPow2x[4];
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} __packed;
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struct cal_tgt_pow_ht {
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u8 tPow2x[14];
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} __packed;
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struct cal_ctl_edge_pwr {
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u8 tPower:6,
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flag:2;
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} __packed;
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struct cal_ctl_data_2g {
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struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
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} __packed;
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struct cal_ctl_data_5g {
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struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
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} __packed;
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struct ar9300_eeprom {
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u8 eepromVersion;
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u8 templateVersion;
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u8 macAddr[6];
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u8 custData[AR9300_CUSTOMER_DATA_SIZE];
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struct ar9300_base_eep_hdr baseEepHeader;
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struct ar9300_modal_eep_header modalHeader2G;
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u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
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struct ar9300_cal_data_per_freq_op_loop
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calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
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u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
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u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
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u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
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u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
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struct cal_tgt_pow_legacy
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calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
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struct cal_tgt_pow_legacy
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calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
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u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
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u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
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struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
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struct ar9300_modal_eep_header modalHeader5G;
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u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
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struct ar9300_cal_data_per_freq_op_loop
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calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
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u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
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u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
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u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
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struct cal_tgt_pow_legacy
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calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
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u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
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u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
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struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
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} __packed;
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#endif
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@ -256,7 +256,9 @@ int ath9k_hw_eeprom_init(struct ath_hw *ah)
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{
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int status;
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if (AR_SREV_9287(ah)) {
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if (AR_SREV_9300_20_OR_LATER(ah))
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ah->eep_ops = &eep_ar9300_ops;
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else if (AR_SREV_9287(ah)) {
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ah->eep_ops = &eep_ar9287_ops;
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} else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
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ah->eep_ops = &eep_4k_ops;
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@ -19,6 +19,7 @@
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#include "../ath.h"
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#include <net/cfg80211.h>
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#include "ar9003_eeprom.h"
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#define AH_USE_EEPROM 0x1
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@ -249,16 +250,20 @@ enum eeprom_param {
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EEP_MINOR_REV,
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EEP_TX_MASK,
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EEP_RX_MASK,
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EEP_FSTCLK_5G,
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EEP_RXGAIN_TYPE,
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EEP_TXGAIN_TYPE,
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EEP_OL_PWRCTRL,
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EEP_TXGAIN_TYPE,
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EEP_RC_CHAIN_MASK,
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EEP_DAC_HPWR_5G,
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EEP_FRAC_N_5G,
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EEP_DEV_TYPE,
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EEP_TEMPSENSE_SLOPE,
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EEP_TEMPSENSE_SLOPE_PAL_ON,
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EEP_PWR_TABLE_OFFSET
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EEP_PWR_TABLE_OFFSET,
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EEP_DRIVE_STRENGTH,
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EEP_INTERNAL_REGULATOR,
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EEP_SWREG
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};
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enum ar5416_rates {
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@ -707,5 +712,7 @@ int ath9k_hw_eeprom_init(struct ath_hw *ah);
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extern const struct eeprom_ops eep_def_ops;
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extern const struct eeprom_ops eep_4k_ops;
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extern const struct eeprom_ops eep_ar9287_ops;
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extern const struct eeprom_ops eep_ar9287_ops;
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extern const struct eeprom_ops eep_ar9300_ops;
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#endif /* EEPROM_H */
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@ -568,6 +568,7 @@ struct ath_hw {
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struct ar5416_eeprom_def def;
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struct ar5416_eeprom_4k map4k;
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struct ar9287_eeprom map9287;
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struct ar9300_eeprom ar9300_eep;
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} eeprom;
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const struct eeprom_ops *eep_ops;
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@ -1070,6 +1070,16 @@ enum {
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#define AR_RTC_RC_COLD_RESET 0x00000004
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#define AR_RTC_RC_WARM_RESET 0x00000008
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/* Crystal Control */
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#define AR_RTC_XTAL_CONTROL 0x7004
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/* Reg Control 0 */
|
||||
#define AR_RTC_REG_CONTROL0 0x7008
|
||||
|
||||
/* Reg Control 1 */
|
||||
#define AR_RTC_REG_CONTROL1 0x700c
|
||||
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
|
||||
|
||||
#define AR_RTC_PLL_CONTROL \
|
||||
((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
|
||||
|
||||
@ -1100,6 +1110,7 @@ enum {
|
||||
#define AR_RTC_SLEEP_CLK \
|
||||
((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
|
||||
#define AR_RTC_FORCE_DERIVED_CLK 0x2
|
||||
#define AR_RTC_FORCE_SWREG_PRD 0x00000004
|
||||
|
||||
#define AR_RTC_FORCE_WAKE \
|
||||
((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user