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gianfar: Don't enable the Filer w/o the Parser

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Under one unusual circumstance it's possible to wrongly set
FILREN without enabling PRSDEP as well in the RCTRL register,
against the hardware specifications.  With the default config
this does not happen because the default Rx offloads (Rx csum
and Rx VLAN) properly enable PRSDEP.  But if anyone disables
all these offloads (via ethtool), we get a wrong configuration
were the Rx flow classification and hashing, and other Filer
based features (e.g. wake-on-filer interrupt) won't work.
This patch fixes the issue.
Also, account for Rx FCB insertion which happens every time
PRSDEP is set.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Claudiu Manoil 2015-10-23 11:41:59 +03:00 committed by David S. Miller
parent 5188f7e5a7
commit 15bf176db1
1 changed files with 2 additions and 2 deletions
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4
drivers/net/ethernet/freescale/gianfar.c
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@ -341,7 +341,7 @@ static void gfar_rx_offload_en(struct gfar_private *priv)
if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
priv->uses_rxfcb = 1; priv->uses_rxfcb = 1;
if (priv->hwts_rx_en) if (priv->hwts_rx_en || priv->rx_filer_enable)
priv->uses_rxfcb = 1; priv->uses_rxfcb = 1;
} }
@ -351,7 +351,7 @@ static void gfar_mac_rx_config(struct gfar_private *priv)
u32 rctrl = 0; u32 rctrl = 0;
if (priv->rx_filer_enable) { if (priv->rx_filer_enable) {
rctrl |= RCTRL_FILREN; rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
/* Program the RIR0 reg with the required distribution */ /* Program the RIR0 reg with the required distribution */
if (priv->poll_mode == GFAR_SQ_POLLING) if (priv->poll_mode == GFAR_SQ_POLLING)
gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0); gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);