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arm64: add comments about EC exception levels

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To make it clear which exceptions can't be taken to EL1 or EL2, add
comments next to the ESR_ELx_EC_* macro definitions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Kristina Martsenko 2018-12-07 18:39:19 +00:00 committed by Will Deacon
parent 26a25c841d
commit 1556065735
1 changed files with 7 additions and 7 deletions
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14
arch/arm64/include/asm/esr.h
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@ -29,23 +29,23 @@
#define ESR_ELx_EC_CP14_MR (0x05) #define ESR_ELx_EC_CP14_MR (0x05)
#define ESR_ELx_EC_CP14_LS (0x06) #define ESR_ELx_EC_CP14_LS (0x06)
#define ESR_ELx_EC_FP_ASIMD (0x07) #define ESR_ELx_EC_FP_ASIMD (0x07)
#define ESR_ELx_EC_CP10_ID (0x08) #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
/* Unallocated EC: 0x09 - 0x0B */ /* Unallocated EC: 0x09 - 0x0B */
#define ESR_ELx_EC_CP14_64 (0x0C) #define ESR_ELx_EC_CP14_64 (0x0C)
/* Unallocated EC: 0x0d */ /* Unallocated EC: 0x0d */
#define ESR_ELx_EC_ILL (0x0E) #define ESR_ELx_EC_ILL (0x0E)
/* Unallocated EC: 0x0F - 0x10 */ /* Unallocated EC: 0x0F - 0x10 */
#define ESR_ELx_EC_SVC32 (0x11) #define ESR_ELx_EC_SVC32 (0x11)
#define ESR_ELx_EC_HVC32 (0x12) #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
#define ESR_ELx_EC_SMC32 (0x13) #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
/* Unallocated EC: 0x14 */ /* Unallocated EC: 0x14 */
#define ESR_ELx_EC_SVC64 (0x15) #define ESR_ELx_EC_SVC64 (0x15)
#define ESR_ELx_EC_HVC64 (0x16) #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
#define ESR_ELx_EC_SMC64 (0x17) #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
#define ESR_ELx_EC_SYS64 (0x18) #define ESR_ELx_EC_SYS64 (0x18)
#define ESR_ELx_EC_SVE (0x19) #define ESR_ELx_EC_SVE (0x19)
/* Unallocated EC: 0x1A - 0x1E */ /* Unallocated EC: 0x1A - 0x1E */
#define ESR_ELx_EC_IMP_DEF (0x1f) #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
#define ESR_ELx_EC_IABT_LOW (0x20) #define ESR_ELx_EC_IABT_LOW (0x20)
#define ESR_ELx_EC_IABT_CUR (0x21) #define ESR_ELx_EC_IABT_CUR (0x21)
#define ESR_ELx_EC_PC_ALIGN (0x22) #define ESR_ELx_EC_PC_ALIGN (0x22)
@ -68,7 +68,7 @@
/* Unallocated EC: 0x36 - 0x37 */ /* Unallocated EC: 0x36 - 0x37 */
#define ESR_ELx_EC_BKPT32 (0x38) #define ESR_ELx_EC_BKPT32 (0x38)
/* Unallocated EC: 0x39 */ /* Unallocated EC: 0x39 */
#define ESR_ELx_EC_VECTOR32 (0x3A) #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
/* Unallocted EC: 0x3B */ /* Unallocted EC: 0x3B */
#define ESR_ELx_EC_BRK64 (0x3C) #define ESR_ELx_EC_BRK64 (0x3C)
/* Unallocated EC: 0x3D - 0x3F */ /* Unallocated EC: 0x3D - 0x3F */