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ASoC: Intel: haswell: Fix power transition refactor
While addressing existing power-cycle limitations for
sound/soc/intel/haswell solution, change brings regression for standard
audio userspace flows e.g.: when using PulseAudio.
Occasional sound-card initialization fail is still better than
permanent audio distortions, so revert the change.
Fixes: 8ec7d60432 ("ASoC: Intel: haswell: Power transition refactor")
Reported-by: Christian Bundy <christianbundy@fraction.io>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20200901153041.14771-1-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Rojewski
Mark Brown
parent
2569231d71
commit
154549558a
@ -243,92 +243,45 @@ static irqreturn_t hsw_irq(int irq, void *context)
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return ret;
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}
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#define CSR_DEFAULT_VALUE 0x8480040E
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#define ISC_DEFAULT_VALUE 0x0
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#define ISD_DEFAULT_VALUE 0x0
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#define IMC_DEFAULT_VALUE 0x7FFF0003
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#define IMD_DEFAULT_VALUE 0x7FFF0003
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#define IPCC_DEFAULT_VALUE 0x0
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#define IPCD_DEFAULT_VALUE 0x0
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#define CLKCTL_DEFAULT_VALUE 0x7FF
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#define CSR2_DEFAULT_VALUE 0x0
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#define LTR_CTRL_DEFAULT_VALUE 0x0
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#define HMD_CTRL_DEFAULT_VALUE 0x0
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static void hsw_set_shim_defaults(struct sst_dsp *sst)
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{
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sst_dsp_shim_write_unlocked(sst, SST_CSR, CSR_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_ISRX, ISC_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_ISRD, ISD_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_IMRX, IMC_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_IMRD, IMD_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_IPCX, IPCC_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_IPCD, IPCD_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_CLKCTL, CLKCTL_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_CSR2, CSR2_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_LTRC, LTR_CTRL_DEFAULT_VALUE);
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sst_dsp_shim_write_unlocked(sst, SST_HMDC, HMD_CTRL_DEFAULT_VALUE);
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}
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/* all clock-gating minus DCLCGE and DTCGE */
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#define SST_VDRTCL2_CG_OTHER 0xB7D
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static void hsw_set_dsp_D3(struct sst_dsp *sst)
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{
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u32 val;
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u32 reg;
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/* disable clock core gating */
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/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg &= ~(SST_VDRTCL2_DCLCGE);
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reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* stall, reset and set 24MHz XOSC */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_24MHZ_LPCS | SST_CSR_STALL | SST_CSR_RST,
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SST_CSR_24MHZ_LPCS | SST_CSR_STALL | SST_CSR_RST);
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/* enable power gating and switch off DRAM & IRAM blocks */
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val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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val |= SST_VDRTCL0_DSRAMPGE_MASK |
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SST_VDRTCL0_ISRAMPGE_MASK;
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val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD);
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writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* DRAM power gating all */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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reg |= SST_VDRTCL0_ISRAMPGE_MASK |
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SST_VDRTCL0_DSRAMPGE_MASK;
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reg &= ~(SST_VDRTCL0_D3SRAMPGD);
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reg |= SST_VDRTCL0_D3PGD;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
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udelay(50);
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/* switch off audio PLL */
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val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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val |= SST_VDRTCL2_APLLSE_MASK;
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writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* PLL shutdown enable */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_APLLSE_MASK;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* disable MCLK */
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/* disable MCLK(clkctl.smos = 0) */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
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SST_CLKCTL_MASK, 0);
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SST_CLKCTL_MASK, 0);
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/* switch clock gating */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_CG_OTHER;
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reg &= ~(SST_VDRTCL2_DTCGE);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* enable DTCGE separatelly */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_DTCGE;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* set shim defaults */
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hsw_set_shim_defaults(sst);
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/* set D3 */
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reg = readl(sst->addr.pci_cfg + SST_PMCS);
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reg |= SST_PMCS_PS_MASK;
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writel(reg, sst->addr.pci_cfg + SST_PMCS);
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/* Set D3 state, delay 50 us */
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val = readl(sst->addr.pci_cfg + SST_PMCS);
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val |= SST_PMCS_PS_MASK;
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writel(val, sst->addr.pci_cfg + SST_PMCS);
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udelay(50);
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/* enable clock core gating */
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/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_DCLCGE;
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reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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udelay(50);
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}
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static void hsw_reset(struct sst_dsp *sst)
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@ -346,62 +299,75 @@ static void hsw_reset(struct sst_dsp *sst)
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SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
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}
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/* recommended CSR state for power-up */
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#define SST_CSR_D0_MASK (0x18A09C0C | SST_CSR_DCS_MASK)
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static int hsw_set_dsp_D0(struct sst_dsp *sst)
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{
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u32 reg;
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int tries = 10;
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u32 reg, fw_dump_bit;
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/* disable clock core gating */
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/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg &= ~(SST_VDRTCL2_DCLCGE);
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reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* switch clock gating */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_CG_OTHER;
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reg &= ~(SST_VDRTCL2_DTCGE);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* set D0 */
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reg = readl(sst->addr.pci_cfg + SST_PMCS);
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reg &= ~(SST_PMCS_PS_MASK);
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writel(reg, sst->addr.pci_cfg + SST_PMCS);
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/* DRAM power gating none */
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/* Disable D3PG (VDRTCTL0.D3PGD = 1) */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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reg &= ~(SST_VDRTCL0_ISRAMPGE_MASK |
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SST_VDRTCL0_DSRAMPGE_MASK);
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reg |= SST_VDRTCL0_D3SRAMPGD;
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reg |= SST_VDRTCL0_D3PGD;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
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mdelay(10);
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/* set shim defaults */
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hsw_set_shim_defaults(sst);
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/* Set D0 state */
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reg = readl(sst->addr.pci_cfg + SST_PMCS);
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reg &= ~SST_PMCS_PS_MASK;
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writel(reg, sst->addr.pci_cfg + SST_PMCS);
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/* restore MCLK */
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/* check that ADSP shim is enabled */
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while (tries--) {
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reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
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if (reg == 0)
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goto finish;
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msleep(1);
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}
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return -ENODEV;
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finish:
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/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
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/* stall DSP core, set clk to 192/96Mhz */
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sst_dsp_shim_update_bits_unlocked(sst,
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SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
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SST_CSR_STALL | SST_CSR_DCS(4));
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/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
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SST_CLKCTL_MASK, SST_CLKCTL_MASK);
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SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
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SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);
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/* PLL shutdown disable */
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/* Stall and reset core, set CSR */
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hsw_reset(sst);
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/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg &= ~(SST_VDRTCL2_APLLSE_MASK);
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reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_D0_MASK, SST_CSR_SBCS0 | SST_CSR_SBCS1 |
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SST_CSR_STALL | SST_CSR_DCS(4));
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udelay(50);
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/* enable clock core gating */
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/* switch on audio PLL */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_DCLCGE;
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reg &= ~SST_VDRTCL2_APLLSE_MASK;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* clear reset */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_RST, 0);
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/* set default power gating control, enable power gating control for all blocks. that is,
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can't be accessed, please enable each block before accessing. */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK;
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/* for D0, always enable the block(DSRAM[0]) used for FW dump */
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fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
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writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* disable DMA finish function for SSP0 & SSP1 */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
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@ -418,6 +384,12 @@ static int hsw_set_dsp_D0(struct sst_dsp *sst)
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sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
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SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
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/* clear IPC registers */
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sst_dsp_shim_write(sst, SST_IPCX, 0x0);
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sst_dsp_shim_write(sst, SST_IPCD, 0x0);
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sst_dsp_shim_write(sst, 0x80, 0x6);
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sst_dsp_shim_write(sst, 0xe0, 0x300a);
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return 0;
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}
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@ -443,6 +415,11 @@ static void hsw_sleep(struct sst_dsp *sst)
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{
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dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
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/* put DSP into reset and stall */
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sst_dsp_shim_update_bits(sst, SST_CSR,
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SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
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SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
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hsw_set_dsp_D3(sst);
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dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
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}
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