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amd/powerplay: Add structures required to report configuration change
Add required structures for amd_powerplay_display_configuration_change Signed-off-by: Eric Yang <eric.yang2@amd.com>
This commit is contained in:
Eric Yang
Alex Deucher
parent
1c9a90820b
commit
14f634110f
@ -239,10 +239,10 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicUVDState);
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cz_hwmgr->display_cfg.cpu_cc6_disable = false;
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cz_hwmgr->display_cfg.cpu_pstate_disable = false;
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cz_hwmgr->display_cfg.nb_pstate_switch_disable = false;
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cz_hwmgr->display_cfg.cpu_pstate_separation_time = 0;
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cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
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cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
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cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
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cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DisableVoltageIsland);
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@ -784,8 +784,11 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
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void *storage, int result)
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{
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SclkDeepSleep)) {
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/* TO DO get from dal PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
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PHM_PlatformCaps_SclkDeepSleep)) {
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uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
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if (clks == 0)
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clks = CZ_MIN_DEEP_SLEEP_SCLK;
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetMinDeepSleepSclk,
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CZ_MIN_DEEP_SLEEP_SCLK);
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@ -873,8 +876,8 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
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const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
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if (hw_data->sys_info.nb_dpm_enable) {
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disable_switch = hw_data->display_cfg.nb_pstate_switch_disable ? true : false;
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enable_low_mem_state = hw_data->display_cfg.nb_pstate_switch_disable ? false : true;
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disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
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enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
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if (pnew_state->action == FORCE_HIGH)
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cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
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@ -1530,18 +1533,18 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
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}
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static void cz_hw_print_display_cfg(
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const struct amd_pp_display_configuration *display_cfg)
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const struct cc6_settings *cc6_settings)
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{
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PP_DBG_LOG("New Display Configuration:\n");
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PP_DBG_LOG(" cpu_cc6_disable: %d\n",
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display_cfg->cpu_cc6_disable);
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cc6_settings->cpu_cc6_disable);
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PP_DBG_LOG(" cpu_pstate_disable: %d\n",
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display_cfg->cpu_pstate_disable);
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cc6_settings->cpu_pstate_disable);
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PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
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display_cfg->nb_pstate_switch_disable);
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cc6_settings->nb_pstate_switch_disable);
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PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
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display_cfg->cpu_pstate_separation_time);
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cc6_settings->cpu_pstate_separation_time);
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}
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static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
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@ -1549,18 +1552,20 @@ static void cz_hw_print_display_cfg(
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struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
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uint32_t data = 0;
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if (hw_data->cc6_setting_changed == true) {
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if (hw_data->cc6_settings.cc6_setting_changed == true) {
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cz_hw_print_display_cfg(&hw_data->display_cfg);
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hw_data->cc6_settings.cc6_setting_changed = false;
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data |= (hw_data->display_cfg.cpu_pstate_separation_time
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cz_hw_print_display_cfg(&hw_data->cc6_settings);
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data |= (hw_data->cc6_settings.cpu_pstate_separation_time
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& PWRMGT_SEPARATION_TIME_MASK)
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<< PWRMGT_SEPARATION_TIME_SHIFT;
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data|= (hw_data->display_cfg.cpu_cc6_disable ? 0x1 : 0x0)
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data|= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
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<< PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
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data|= (hw_data->display_cfg.cpu_pstate_disable ? 0x1 : 0x0)
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data|= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
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<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
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PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
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@ -1569,30 +1574,39 @@ static void cz_hw_print_display_cfg(
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetDisplaySizePowerParams,
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data);
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hw_data->cc6_setting_changed = false;
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}
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return 0;
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}
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static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
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bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
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{
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{
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struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
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if (separation_time != hw_data->display_cfg.cpu_pstate_separation_time
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|| cc6_disable != hw_data->display_cfg.cpu_cc6_disable
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|| pstate_disable != hw_data->display_cfg.cpu_pstate_disable
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|| pstate_switch_disable != hw_data->display_cfg.nb_pstate_switch_disable) {
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if (separation_time !=
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hw_data->cc6_settings.cpu_pstate_separation_time
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|| cc6_disable !=
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hw_data->cc6_settings.cpu_cc6_disable
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|| pstate_disable !=
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hw_data->cc6_settings.cpu_pstate_disable
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|| pstate_switch_disable !=
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hw_data->cc6_settings.nb_pstate_switch_disable) {
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hw_data->display_cfg.cpu_pstate_separation_time = separation_time;
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hw_data->display_cfg.cpu_cc6_disable = cc6_disable;
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hw_data->display_cfg.cpu_pstate_disable = pstate_disable;
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hw_data->display_cfg.nb_pstate_switch_disable = pstate_switch_disable;
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hw_data->cc6_setting_changed = true;
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hw_data->cc6_settings.cc6_setting_changed = true;
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hw_data->cc6_settings.cpu_pstate_separation_time =
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separation_time;
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hw_data->cc6_settings.cpu_cc6_disable =
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cc6_disable;
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hw_data->cc6_settings.cpu_pstate_disable =
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pstate_disable;
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hw_data->cc6_settings.nb_pstate_switch_disable =
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pstate_switch_disable;
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}
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return 0;
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}
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@ -176,6 +176,14 @@ struct cz_power_state {
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#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */
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#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */
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struct cc6_settings {
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bool cc6_setting_changed;
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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};
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struct cz_hwmgr {
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uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
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uint32_t dpm_interval;
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@ -238,7 +246,7 @@ struct cz_hwmgr {
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uint32_t highest_valid;
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uint32_t high_voltage_threshold;
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uint32_t is_nb_dpm_enabled;
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struct amd_pp_display_configuration display_cfg; /* set by DAL */
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struct cc6_settings cc6_settings;
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uint32_t is_voltage_island_enabled;
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bool pgacpinit;
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@ -304,7 +312,6 @@ struct cz_hwmgr {
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uint32_t max_sclk_level;
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uint32_t num_of_clk_entries;
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bool cc6_setting_changed;
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};
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struct pp_hwmgr;
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@ -249,16 +249,21 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
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int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
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const struct amd_pp_display_configuration *display_config)
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{
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if (hwmgr == NULL || hwmgr->hwmgr_func->store_cc6_data == NULL)
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if (hwmgr == NULL)
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return -EINVAL;
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hwmgr->display_config = *display_config;
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/* to do pass other display configuration in furture */
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return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
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display_config->cpu_pstate_separation_time,
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display_config->cpu_cc6_disable,
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display_config->cpu_pstate_disable,
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display_config->nb_pstate_switch_disable);
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if (hwmgr->hwmgr_func->store_cc6_data)
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hwmgr->hwmgr_func->store_cc6_data(hwmgr,
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display_config->cpu_pstate_separation_time,
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display_config->cpu_cc6_disable,
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display_config->cpu_pstate_disable,
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display_config->nb_pstate_switch_disable);
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return 0;
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}
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int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
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@ -130,12 +130,85 @@ struct amd_pp_init {
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uint32_t chip_id;
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uint32_t rev_id;
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};
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enum amd_pp_display_config_type{
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AMD_PP_DisplayConfigType_None = 0,
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AMD_PP_DisplayConfigType_DP54 ,
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AMD_PP_DisplayConfigType_DP432 ,
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AMD_PP_DisplayConfigType_DP324 ,
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AMD_PP_DisplayConfigType_DP27,
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AMD_PP_DisplayConfigType_DP243,
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AMD_PP_DisplayConfigType_DP216,
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AMD_PP_DisplayConfigType_DP162,
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AMD_PP_DisplayConfigType_HDMI6G ,
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AMD_PP_DisplayConfigType_HDMI297 ,
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AMD_PP_DisplayConfigType_HDMI162,
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AMD_PP_DisplayConfigType_LVDS,
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AMD_PP_DisplayConfigType_DVI,
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AMD_PP_DisplayConfigType_WIRELESS,
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AMD_PP_DisplayConfigType_VGA
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};
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struct single_display_configuration
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{
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uint32_t controller_index;
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uint32_t controller_id;
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uint32_t signal_type;
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uint32_t display_state;
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/* phy id for the primary internal transmitter */
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uint8_t primary_transmitter_phyi_d;
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/* bitmap with the active lanes */
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uint8_t primary_transmitter_active_lanemap;
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/* phy id for the secondary internal transmitter (for dual-link dvi) */
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uint8_t secondary_transmitter_phy_id;
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/* bitmap with the active lanes */
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uint8_t secondary_transmitter_active_lanemap;
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/* misc phy settings for SMU. */
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uint32_t config_flags;
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uint32_t display_type;
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uint32_t view_resolution_cx;
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uint32_t view_resolution_cy;
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enum amd_pp_display_config_type displayconfigtype;
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uint32_t vertical_refresh; /* for active display */
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};
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#define MAX_NUM_DISPLAY 32
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struct amd_pp_display_configuration {
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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uint32_t num_display; /* total number of display*/
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uint32_t num_path_including_non_display;
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uint32_t crossfire_display_index;
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uint32_t min_mem_set_clock;
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uint32_t min_core_set_clock;
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/* unit 10KHz x bit*/
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uint32_t min_bus_bandwidth;
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/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
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uint32_t min_core_set_clock_in_sr;
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struct single_display_configuration displays[MAX_NUM_DISPLAY];
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uint32_t vrefresh; /* for active display*/
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uint32_t min_vblank_time; /* for active display*/
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bool multi_monitor_in_sync;
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/* Controller Index of primary display - used in MCLK SMC switching hang
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* SW Workaround*/
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uint32_t crtc_index;
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/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
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uint32_t line_time_in_us;
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bool invalid_vblank_time;
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uint32_t display_clk;
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/*
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* for given display configuration if multimonitormnsync == false then
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* Memory clock DPMS with this latency or below is allowed, DPMS with
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* higher latency not allowed.
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*/
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uint32_t dce_tolerable_mclk_in_active_latency;
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};
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struct amd_pp_dal_clock_info {
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@ -601,6 +601,7 @@ struct pp_hwmgr {
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struct pp_power_state *request_ps;
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struct pp_power_state *boot_ps;
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struct pp_power_state *uvd_ps;
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struct amd_pp_display_configuration display_config;
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};
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