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ARC: Atomic/bitops/cmpxchg/barriers
This covers the UP / SMP (with no hardware assist for atomic r-m-w) as well as ARC700 LLOCK/SCOND insns based. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
ac4c244d4e
commit
14e968bad7
232
arch/arc/include/asm/atomic.h
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232
arch/arc/include/asm/atomic.h
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_ATOMIC_H
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#define _ASM_ARC_ATOMIC_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#define atomic_read(v) ((v)->counter)
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#ifdef CONFIG_ARC_HAS_LLSC
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#define atomic_set(v, i) (((v)->counter) = (i))
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" add %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */
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: "r"(&v->counter), "ir"(i)
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: "cc");
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" sub %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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}
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/* add and also return the new value */
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" add %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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return temp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" sub %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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return temp;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bic %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(addr), "ir"(mask)
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: "cc");
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#ifndef CONFIG_SMP
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/* violating atomic_xxx API locking protocol in UP for optimization sake */
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#define atomic_set(v, i) (((v)->counter) = (i))
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#else
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static inline void atomic_set(atomic_t *v, int i)
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{
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/*
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* Independent of hardware support, all of the atomic_xxx() APIs need
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* to follow the same locking rules to make sure that a "hardware"
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* atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
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* sequence
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*
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* Thus atomic_set() despite being 1 insn (and seemingly atomic)
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* requires the locking.
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*/
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter = i;
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atomic_ops_unlock(flags);
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}
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#endif
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/*
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter += i;
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atomic_ops_unlock(flags);
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter -= i;
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atomic_ops_unlock(flags);
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long flags;
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unsigned long temp;
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atomic_ops_lock(flags);
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temp = v->counter;
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temp += i;
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v->counter = temp;
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atomic_ops_unlock(flags);
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return temp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long flags;
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unsigned long temp;
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atomic_ops_lock(flags);
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temp = v->counter;
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temp -= i;
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v->counter = temp;
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atomic_ops_unlock(flags);
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return temp;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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*addr &= ~mask;
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atomic_ops_unlock(flags);
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}
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#endif /* !CONFIG_ARC_HAS_LLSC */
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v
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*/
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#define __atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c)\
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c = old; \
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c; \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#define atomic_inc(v) atomic_add(1, v)
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#define atomic_dec(v) atomic_sub(1, v)
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#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0)
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#define ATOMIC_INIT(i) { (i) }
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#include <asm-generic/atomic64.h>
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#endif
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#endif
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#endif
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42
arch/arc/include/asm/barrier.h
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42
arch/arc/include/asm/barrier.h
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@ -0,0 +1,42 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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/* TODO-vineetg: Need to see what this does, don't we need sync anywhere */
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define read_barrier_depends() mb()
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/* TODO-vineetg verify the correctness of macros here */
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#endif
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#endif
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516
arch/arc/include/asm/bitops.h
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516
arch/arc/include/asm/bitops.h
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@ -0,0 +1,516 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_BITOPS_H
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#define _ASM_BITOPS_H
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/compiler.h>
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/*
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* Hardware assisted read-modify-write using ARC700 LLOCK/SCOND insns.
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* The Kconfig glue ensures that in SMP, this is only set if the container
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* SoC/platform has cross-core coherent LLOCK/SCOND
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*/
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#if defined(CONFIG_ARC_HAS_LLSC)
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static inline void set_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bset %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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}
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static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bclr %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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}
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static inline void change_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bxor %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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}
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/*
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* Semantically:
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* Test the bit
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* if clear
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* set it and return 0 (old value)
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* else
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* return 1 (old value).
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*
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* Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
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* and the old value of bit is returned
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*/
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static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long old, temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%2] \n"
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" bset %1, %0, %3 \n"
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" scond %1, [%2] \n"
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" bnz 1b \n"
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: "=&r"(old), "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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return (old & (1 << nr)) != 0;
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}
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static inline int
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test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int old, temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%2] \n"
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" bclr %1, %0, %3 \n"
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" scond %1, [%2] \n"
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" bnz 1b \n"
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: "=&r"(old), "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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return (old & (1 << nr)) != 0;
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}
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static inline int
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test_and_change_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int old, temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%2] \n"
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" bxor %1, %0, %3 \n"
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" scond %1, [%2] \n"
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" bnz 1b \n"
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: "=&r"(old), "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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return (old & (1 << nr)) != 0;
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#include <asm/smp.h>
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/*
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*
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* There's "significant" micro-optimization in writing our own variants of
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* bitops (over generic variants)
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*
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* (1) The generic APIs have "signed" @nr while we have it "unsigned"
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* This avoids extra code to be generated for pointer arithmatic, since
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* is "not sure" that index is NOT -ve
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* (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
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* only consider bottom 5 bits of @nr, so NO need to mask them off.
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* (GCC Quirk: however for constant @nr we still need to do the masking
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* at compile time)
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*/
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static inline void set_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long temp, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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bitops_lock(flags);
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temp = *m;
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*m = temp | (1UL << nr);
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bitops_unlock(flags);
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}
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static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long temp, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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bitops_lock(flags);
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temp = *m;
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*m = temp & ~(1UL << nr);
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bitops_unlock(flags);
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}
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static inline void change_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long temp, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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bitops_lock(flags);
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temp = *m;
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*m = temp ^ (1UL << nr);
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bitops_unlock(flags);
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}
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|
||||
static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long old, flags;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
bitops_lock(flags);
|
||||
|
||||
old = *m;
|
||||
*m = old | (1 << nr);
|
||||
|
||||
bitops_unlock(flags);
|
||||
|
||||
return (old & (1 << nr)) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long old, flags;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
bitops_lock(flags);
|
||||
|
||||
old = *m;
|
||||
*m = old & ~(1 << nr);
|
||||
|
||||
bitops_unlock(flags);
|
||||
|
||||
return (old & (1 << nr)) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_and_change_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long old, flags;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
bitops_lock(flags);
|
||||
|
||||
old = *m;
|
||||
*m = old ^ (1 << nr);
|
||||
|
||||
bitops_unlock(flags);
|
||||
|
||||
return (old & (1 << nr)) != 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARC_HAS_LLSC */
|
||||
|
||||
/***************************************
|
||||
* Non atomic variants
|
||||
**************************************/
|
||||
|
||||
static inline void __set_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long temp;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
temp = *m;
|
||||
*m = temp | (1UL << nr);
|
||||
}
|
||||
|
||||
static inline void __clear_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long temp;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
temp = *m;
|
||||
*m = temp & ~(1UL << nr);
|
||||
}
|
||||
|
||||
static inline void __change_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long temp;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
temp = *m;
|
||||
*m = temp ^ (1UL << nr);
|
||||
}
|
||||
|
||||
static inline int
|
||||
__test_and_set_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long old;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
old = *m;
|
||||
*m = old | (1 << nr);
|
||||
|
||||
return (old & (1 << nr)) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
__test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long old;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
old = *m;
|
||||
*m = old & ~(1 << nr);
|
||||
|
||||
return (old & (1 << nr)) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
__test_and_change_bit(unsigned long nr, volatile unsigned long *m)
|
||||
{
|
||||
unsigned long old;
|
||||
m += nr >> 5;
|
||||
|
||||
if (__builtin_constant_p(nr))
|
||||
nr &= 0x1f;
|
||||
|
||||
old = *m;
|
||||
*m = old ^ (1 << nr);
|
||||
|
||||
return (old & (1 << nr)) != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This routine doesn't need to be atomic.
|
||||
*/
|
||||
static inline int
|
||||
__constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
|
||||
{
|
||||
return ((1UL << (nr & 31)) &
|
||||
(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
__test_bit(unsigned int nr, const volatile unsigned long *addr)
|
||||
{
|
||||
unsigned long mask;
|
||||
|
||||
addr += nr >> 5;
|
||||
|
||||
/* ARC700 only considers 5 bits in bit-fiddling insn */
|
||||
mask = 1 << nr;
|
||||
|
||||
return ((mask & *addr) != 0);
|
||||
}
|
||||
|
||||
#define test_bit(nr, addr) (__builtin_constant_p(nr) ? \
|
||||
__constant_test_bit((nr), (addr)) : \
|
||||
__test_bit((nr), (addr)))
|
||||
|
||||
/*
|
||||
* Count the number of zeros, starting from MSB
|
||||
* Helper for fls( ) friends
|
||||
* This is a pure count, so (1-32) or (0-31) doesn't apply
|
||||
* It could be 0 to 32, based on num of 0's in there
|
||||
* clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
|
||||
*/
|
||||
static inline __attribute__ ((const)) int clz(unsigned int x)
|
||||
{
|
||||
unsigned int res;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" norm.f %0, %1 \n"
|
||||
" mov.n %0, 0 \n"
|
||||
" add.p %0, %0, 1 \n"
|
||||
: "=r"(res)
|
||||
: "r"(x)
|
||||
: "cc");
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline int constant_fls(int x)
|
||||
{
|
||||
int r = 32;
|
||||
|
||||
if (!x)
|
||||
return 0;
|
||||
if (!(x & 0xffff0000u)) {
|
||||
x <<= 16;
|
||||
r -= 16;
|
||||
}
|
||||
if (!(x & 0xff000000u)) {
|
||||
x <<= 8;
|
||||
r -= 8;
|
||||
}
|
||||
if (!(x & 0xf0000000u)) {
|
||||
x <<= 4;
|
||||
r -= 4;
|
||||
}
|
||||
if (!(x & 0xc0000000u)) {
|
||||
x <<= 2;
|
||||
r -= 2;
|
||||
}
|
||||
if (!(x & 0x80000000u)) {
|
||||
x <<= 1;
|
||||
r -= 1;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* fls = Find Last Set in word
|
||||
* @result: [1-32]
|
||||
* fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
|
||||
*/
|
||||
static inline __attribute__ ((const)) int fls(unsigned long x)
|
||||
{
|
||||
if (__builtin_constant_p(x))
|
||||
return constant_fls(x);
|
||||
|
||||
return 32 - clz(x);
|
||||
}
|
||||
|
||||
/*
|
||||
* __fls: Similar to fls, but zero based (0-31)
|
||||
*/
|
||||
static inline __attribute__ ((const)) int __fls(unsigned long x)
|
||||
{
|
||||
if (!x)
|
||||
return 0;
|
||||
else
|
||||
return fls(x) - 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* ffs = Find First Set in word (LSB to MSB)
|
||||
* @result: [1-32], 0 if all 0's
|
||||
*/
|
||||
#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
|
||||
|
||||
/*
|
||||
* __ffs: Similar to ffs, but zero based (0-31)
|
||||
*/
|
||||
static inline __attribute__ ((const)) int __ffs(unsigned long word)
|
||||
{
|
||||
if (!word)
|
||||
return word;
|
||||
|
||||
return ffs(word) - 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* ffz = Find First Zero in word.
|
||||
* @return:[0-31], 32 if all 1's
|
||||
*/
|
||||
#define ffz(x) __ffs(~(x))
|
||||
|
||||
/* TODO does this affect uni-processor code */
|
||||
#define smp_mb__before_clear_bit() barrier()
|
||||
#define smp_mb__after_clear_bit() barrier()
|
||||
|
||||
#include <asm-generic/bitops/hweight.h>
|
||||
#include <asm-generic/bitops/fls64.h>
|
||||
#include <asm-generic/bitops/sched.h>
|
||||
#include <asm-generic/bitops/lock.h>
|
||||
|
||||
#include <asm-generic/bitops/find.h>
|
||||
#include <asm-generic/bitops/le.h>
|
||||
#include <asm-generic/bitops/ext2-atomic-setbit.h>
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif
|
||||
143
arch/arc/include/asm/cmpxchg.h
Normal file
143
arch/arc/include/asm/cmpxchg.h
Normal file
@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARC_CMPXCHG_H
|
||||
#define __ASM_ARC_CMPXCHG_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/smp.h>
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_LLSC
|
||||
|
||||
static inline unsigned long
|
||||
__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
|
||||
{
|
||||
unsigned long prev;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: llock %0, [%1] \n"
|
||||
" brne %0, %2, 2f \n"
|
||||
" scond %3, [%1] \n"
|
||||
" bnz 1b \n"
|
||||
"2: \n"
|
||||
: "=&r"(prev)
|
||||
: "r"(ptr), "ir"(expected),
|
||||
"r"(new) /* can't be "ir". scond can't take limm for "b" */
|
||||
: "cc");
|
||||
|
||||
return prev;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline unsigned long
|
||||
__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
|
||||
{
|
||||
unsigned long flags;
|
||||
int prev;
|
||||
volatile unsigned long *p = ptr;
|
||||
|
||||
atomic_ops_lock(flags);
|
||||
prev = *p;
|
||||
if (prev == expected)
|
||||
*p = new;
|
||||
atomic_ops_unlock(flags);
|
||||
return prev;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARC_HAS_LLSC */
|
||||
|
||||
#define cmpxchg(ptr, o, n) ((typeof(*(ptr)))__cmpxchg((ptr), \
|
||||
(unsigned long)(o), (unsigned long)(n)))
|
||||
|
||||
/*
|
||||
* Since not supported natively, ARC cmpxchg() uses atomic_ops_lock (UP/SMP)
|
||||
* just to gaurantee semantics.
|
||||
* atomic_cmpxchg() needs to use the same locks as it's other atomic siblings
|
||||
* which also happens to be atomic_ops_lock.
|
||||
*
|
||||
* Thus despite semantically being different, implementation of atomic_cmpxchg()
|
||||
* is same as cmpxchg().
|
||||
*/
|
||||
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
|
||||
|
||||
|
||||
/*
|
||||
* xchg (reg with memory) based on "Native atomic" EX insn
|
||||
*/
|
||||
static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
|
||||
int size)
|
||||
{
|
||||
extern unsigned long __xchg_bad_pointer(void);
|
||||
|
||||
switch (size) {
|
||||
case 4:
|
||||
__asm__ __volatile__(
|
||||
" ex %0, [%1] \n"
|
||||
: "+r"(val)
|
||||
: "r"(ptr)
|
||||
: "memory");
|
||||
|
||||
return val;
|
||||
}
|
||||
return __xchg_bad_pointer();
|
||||
}
|
||||
|
||||
#define _xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
|
||||
sizeof(*(ptr))))
|
||||
|
||||
/*
|
||||
* On ARC700, EX insn is inherently atomic, so by default "vanilla" xchg() need
|
||||
* not require any locking. However there's a quirk.
|
||||
* ARC lacks native CMPXCHG, thus emulated (see above), using external locking -
|
||||
* incidently it "reuses" the same atomic_ops_lock used by atomic APIs.
|
||||
* Now, llist code uses cmpxchg() and xchg() on same data, so xchg() needs to
|
||||
* abide by same serializing rules, thus ends up using atomic_ops_lock as well.
|
||||
*
|
||||
* This however is only relevant if SMP and/or ARC lacks LLSC
|
||||
* if (UP or LLSC)
|
||||
* xchg doesn't need serialization
|
||||
* else <==> !(UP or LLSC) <==> (!UP and !LLSC) <==> (SMP and !LLSC)
|
||||
* xchg needs serialization
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP)
|
||||
|
||||
#define xchg(ptr, with) \
|
||||
({ \
|
||||
unsigned long flags; \
|
||||
typeof(*(ptr)) old_val; \
|
||||
\
|
||||
atomic_ops_lock(flags); \
|
||||
old_val = _xchg(ptr, with); \
|
||||
atomic_ops_unlock(flags); \
|
||||
old_val; \
|
||||
})
|
||||
|
||||
#else
|
||||
|
||||
#define xchg(ptr, with) _xchg(ptr, with)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* "atomic" variant of xchg()
|
||||
* REQ: It needs to follow the same serialization rules as other atomic_xxx()
|
||||
* Since xchg() doesn't always do that, it would seem that following defintion
|
||||
* is incorrect. But here's the rationale:
|
||||
* SMP : Even xchg() takes the atomic_ops_lock, so OK.
|
||||
* LLSC: atomic_ops_lock are not relevent at all (even if SMP, since LLSC
|
||||
* is natively "SMP safe", no serialization required).
|
||||
* UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg()
|
||||
* could clobber them. atomic_xchg() itself would be 1 insn, so it
|
||||
* can't be clobbered by others. Thus no serialization required when
|
||||
* atomic_xchg is involved.
|
||||
*/
|
||||
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
|
||||
|
||||
#endif
|
||||
34
arch/arc/include/asm/smp.h
Normal file
34
arch/arc/include/asm/smp.h
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARC_SMP_H
|
||||
#define __ASM_ARC_SMP_H
|
||||
|
||||
/*
|
||||
* ARC700 doesn't support atomic Read-Modify-Write ops.
|
||||
* Originally Interrupts had to be disabled around code to gaurantee atomicity.
|
||||
* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
|
||||
* based on retry-if-irq-in-atomic (with hardware assist).
|
||||
* However despite these, we provide the IRQ disabling variant
|
||||
*
|
||||
* (1) These insn were introduced only in 4.10 release. So for older released
|
||||
* support needed.
|
||||
*/
|
||||
#ifndef CONFIG_ARC_HAS_LLSC
|
||||
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
#define atomic_ops_lock(flags) local_irq_save(flags)
|
||||
#define atomic_ops_unlock(flags) local_irq_restore(flags)
|
||||
|
||||
#define bitops_lock(flags) local_irq_save(flags)
|
||||
#define bitops_unlock(flags) local_irq_restore(flags)
|
||||
|
||||
#endif /* !CONFIG_ARC_HAS_LLSC */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user