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OMAPDSS: Correct DISPC_IRQ bit definitions for LCD3
The DISPC_IRQ bit definitions pertaining to channel LCD3 as DISPC_IRQ_VSYNC3, DISPC_IRQ_SYNC_LOST3, DISPC_IRQ_ACBIAS_COUNT_STAT3 AND DISPC_IRQ_FRAMEDONE3 which were incorrectly set in previous LCD3 patches have been corrected here. Reported-by: Mark Tyler <mark.tyler@ti.com> Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -48,10 +48,10 @@
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#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
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#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
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#define DISPC_IRQ_FRAMEDONETV (1 << 24)
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#define DISPC_IRQ_FRAMEDONETV (1 << 24)
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#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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#define DISPC_IRQ_FRAMEDONE3 (1 << 26)
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#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
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#define DISPC_IRQ_VSYNC3 (1 << 27)
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#define DISPC_IRQ_VSYNC3 (1 << 28)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 28)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
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#define DISPC_IRQ_SYNC_LOST3 (1 << 29)
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#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
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struct omap_dss_device;
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struct omap_dss_device;
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struct omap_overlay_manager;
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struct omap_overlay_manager;
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