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MIPS: dump_tlb: Use tlbr hazard macros

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Use the new tlb read hazard macros from <asm/hazards.h> rather than the
local BARRIER() macro which uses 7 ops regardless of the kernel
configuration.

We use mtc0_tlbr_hazard for the hazard between mtc0 to the index
register and the tlbr, and tlb_read_hazard for the hazard between the
tlbr and the mfc0 of the TLB registers written by tlbr.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10074/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan 2015-05-19 09:50:32 +01:00 committed by Ralf Baechle
parent 8ab6abcb6a
commit 137877e432
1 changed files with 3 additions and 8 deletions
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11
arch/mips/lib/dump_tlb.c
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@ -7,6 +7,7 @@
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/hazards.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
@ -40,12 +41,6 @@ static inline const char *msk2str(unsigned int mask)
return "";
}
#define BARRIER() \
__asm__ __volatile__( \
".set\tnoreorder\n\t" \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
".set\treorder");
static void dump_tlb(int first, int last)
{
unsigned long s_entryhi, entryhi, asid;
@ -59,9 +54,9 @@ static void dump_tlb(int first, int last)
for (i = first; i <= last; i++) {
write_c0_index(i);
BARRIER();
mtc0_tlbr_hazard();
tlb_read();
BARRIER();
tlb_read_hazard();
pagemask = read_c0_pagemask();
entryhi = read_c0_entryhi();
entrylo0 = read_c0_entrylo0();