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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev

Browse Source 
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
  sata_fsl,mv,nv: prepare for NCQ command completion update
  ata: Convert pci_table entries to PCI_VDEVICE (if PCI_ANY_ID is used)
  libata: more PCI IDs for jmicron controllers
  ata_piix: fix locking around SIDPR access
  [libata] update blacklist for new hyphenated pattern ranges (v2)
  libata: allow hyphenated pattern ranges
  ata_generic: drop hard coded DMA force logic for CENATEK
  [libata] ahci: Fix warning: comparison between 'enum <anonymous>' and 'enum <anonymous>'
  [libata] add ATA_CMD_DSM to ata_get_cmd_descript
  [libata] Add Samsung PATA controller driver, pata_samsung_cf
  [libata] Add 460EX on-chip SATA driver, sata_dwc_460ex
  libata: reduce blacklist size even more (v2)
  libata: reduce blacklist size (v2)
  libata: glob_match for ata_device_blacklist (v2)
  ahci_platform: Remove unneeded ahci_driver.probe assignment
  ahci_platform: Provide for vendor specific init
This commit is contained in:
Linus Torvalds 2010-08-06 09:20:19 -07:00
commit 132a4edb2b
17 changed files with 2615 additions and 158 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/ata/Kconfig
View File

@ -187,6 +187,15 @@ config ATA_PIIX
If unsure, say N.
config SATA_DWC
tristate "DesignWare Cores SATA support"
depends on 460EX
help
This option enables support for the on-chip SATA controller of the
AppliedMicro processor 460EX.
If unsure, say N.
config SATA_MV
tristate "Marvell SATA support"
help
@ -796,6 +805,15 @@ config PATA_RZ1000
If unsure, say N.
config PATA_SAMSUNG_CF
tristate "Samsung SoC PATA support"
depends on SAMSUNG_DEV_IDE
help
This option enables basic support for Samsung's S3C/S5P board
PATA controllers via the new ATA layer
If unsure, say N.
config PATA_WINBOND_VLB
tristate "Winbond W83759A VLB PATA support (Experimental)"
depends on ISA && EXPERIMENTAL

2
drivers/ata/Makefile
View File

@ -7,6 +7,7 @@ obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
# SFF w/ custom DMA
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
@ -87,6 +88,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
obj-$(CONFIG_PATA_QDI) += pata_qdi.o
obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o
# Should be last but two libata driver

2
drivers/ata/ahci.c
View File

@ -1042,7 +1042,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
VPRINTK("ENTER\n");
WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
if (!printed_version++)
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

26
drivers/ata/ahci_platform.c
View File

@ -54,19 +54,13 @@ static int __init ahci_probe(struct platform_device *pdev)
return -EINVAL;
}
if (pdata && pdata->init) {
rc = pdata->init(dev);
if (rc)
return rc;
}
if (pdata && pdata->ata_port_info)
pi = *pdata->ata_port_info;
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
if (!hpriv) {
rc = -ENOMEM;
goto err0;
dev_err(dev, "can't alloc ahci_host_priv\n");
return -ENOMEM;
}
hpriv->flags |= (unsigned long)pi.private_data;
@ -74,8 +68,19 @@ static int __init ahci_probe(struct platform_device *pdev)
hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
if (!hpriv->mmio) {
dev_err(dev, "can't map %pR\n", mem);
rc = -ENOMEM;
goto err0;
return -ENOMEM;
}
/*
* Some platforms might need to prepare for mmio region access,
* which could be done in the following init call. So, the mmio
* region shouldn't be accessed before init (if provided) has
* returned successfully.
*/
if (pdata && pdata->init) {
rc = pdata->init(dev, hpriv->mmio);
if (rc)
return rc;
}
ahci_save_initial_config(dev, hpriv,
@ -166,7 +171,6 @@ static int __devexit ahci_remove(struct platform_device *pdev)
}
static struct platform_driver ahci_driver = {
.probe = ahci_probe,
.remove = __devexit_p(ahci_remove),
.driver = {
.name = "ahci",

4
drivers/ata/ata_generic.c
View File

@ -54,7 +54,6 @@ static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
const struct pci_device_id *id = ap->host->private_data;
int dma_enabled = 0;
struct ata_device *dev;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
if (id->driver_data & ATA_GEN_FORCE_DMA) {
dma_enabled = 0xff;
@ -63,9 +62,6 @@ static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
}
if (pdev->vendor == PCI_VENDOR_ID_CENATEK)
dma_enabled = 0xFF;
ata_for_each_dev(dev, link, ENABLED) {
/* We don't really care */
dev->pio_mode = XFER_PIO_0;

8
drivers/ata/ata_piix.c
View File

@ -158,6 +158,7 @@ struct piix_map_db {
struct piix_host_priv {
const int *map;
u32 saved_iocfg;
spinlock_t sidpr_lock; /* FIXME: remove once locking in EH is fixed */
void __iomem *sidpr;
};
@ -951,12 +952,15 @@ static int piix_sidpr_scr_read(struct ata_link *link,
unsigned int reg, u32 *val)
{
struct piix_host_priv *hpriv = link->ap->host->private_data;
unsigned long flags;
if (reg >= ARRAY_SIZE(piix_sidx_map))
return -EINVAL;
spin_lock_irqsave(&hpriv->sidpr_lock, flags);
piix_sidpr_sel(link, reg);
*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
return 0;
}
@ -964,12 +968,15 @@ static int piix_sidpr_scr_write(struct ata_link *link,
unsigned int reg, u32 val)
{
struct piix_host_priv *hpriv = link->ap->host->private_data;
unsigned long flags;
if (reg >= ARRAY_SIZE(piix_sidx_map))
return -EINVAL;
spin_lock_irqsave(&hpriv->sidpr_lock, flags);
piix_sidpr_sel(link, reg);
iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
return 0;
}
@ -1566,6 +1573,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
if (!hpriv)
return -ENOMEM;
spin_lock_init(&hpriv->sidpr_lock);
/* Save IOCFG, this will be used for cable detection, quirk
* detection and restoration on detach. This is necessary

159
drivers/ata/libata-core.c
View File

@ -4167,15 +4167,13 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
{ "WDC AC23200L", "21.10N21", ATA_HORKAGE_NODMA },
{ "Compaq CRD-8241B", NULL, ATA_HORKAGE_NODMA },
{ "CRD-8400B", NULL, ATA_HORKAGE_NODMA },
{ "CRD-8480B", NULL, ATA_HORKAGE_NODMA },
{ "CRD-8482B", NULL, ATA_HORKAGE_NODMA },
{ "CRD-848[02]B", NULL, ATA_HORKAGE_NODMA },
{ "CRD-84", NULL, ATA_HORKAGE_NODMA },
{ "SanDisk SDP3B", NULL, ATA_HORKAGE_NODMA },
{ "SanDisk SDP3B-64", NULL, ATA_HORKAGE_NODMA },
{ "SANYO CD-ROM CRD", NULL, ATA_HORKAGE_NODMA },
{ "HITACHI CDR-8", NULL, ATA_HORKAGE_NODMA },
{ "HITACHI CDR-8335", NULL, ATA_HORKAGE_NODMA },
{ "HITACHI CDR-8435", NULL, ATA_HORKAGE_NODMA },
{ "HITACHI CDR-8[34]35",NULL, ATA_HORKAGE_NODMA },
{ "Toshiba CD-ROM XM-6202B", NULL, ATA_HORKAGE_NODMA },
{ "TOSHIBA CD-ROM XM-1702BC", NULL, ATA_HORKAGE_NODMA },
{ "CD-532E-A", NULL, ATA_HORKAGE_NODMA },
@ -4211,70 +4209,16 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
{ "OCZ CORE_SSD", "02.10104", ATA_HORKAGE_NONCQ },
/* Seagate NCQ + FLUSH CACHE firmware bug */
{ "ST31500341AS", "SD15", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31500341AS", "SD16", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31500341AS", "SD17", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31500341AS", "SD18", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31500341AS", "SD19", ATA_HORKAGE_NONCQ |
{ "ST31500341AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31000333AS", "SD15", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31000333AS", "SD16", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31000333AS", "SD17", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31000333AS", "SD18", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST31000333AS", "SD19", ATA_HORKAGE_NONCQ |
{ "ST31000333AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640623AS", "SD15", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640623AS", "SD16", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640623AS", "SD17", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640623AS", "SD18", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640623AS", "SD19", ATA_HORKAGE_NONCQ |
{ "ST3640[36]23AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640323AS", "SD15", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640323AS", "SD16", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640323AS", "SD17", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640323AS", "SD18", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3640323AS", "SD19", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320813AS", "SD15", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320813AS", "SD16", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320813AS", "SD17", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320813AS", "SD18", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320813AS", "SD19", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320613AS", "SD15", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320613AS", "SD16", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320613AS", "SD17", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320613AS", "SD18", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
{ "ST3320613AS", "SD19", ATA_HORKAGE_NONCQ |
{ "ST3320[68]13AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
ATA_HORKAGE_FIRMWARE_WARN },
/* Blacklist entries taken from Silicon Image 3124/3132
@ -4303,12 +4247,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
/* Devices which get the IVB wrong */
{ "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, },
/* Maybe we should just blacklist TSSTcorp... */
{ "TSSTcorp CDDVDW SH-S202H", "SB00", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202H", "SB01", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202J", "SB00", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202J", "SB01", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202N", "SB00", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202N", "SB01", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202[HJN]", "SB0[01]", ATA_HORKAGE_IVB, },
/* Devices that do not need bridging limits applied */
{ "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, },
@ -4326,29 +4265,73 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
{ }
};
static int strn_pattern_cmp(const char *patt, const char *name, int wildchar)
/**
* glob_match - match a text string against a glob-style pattern
* @text: the string to be examined
* @pattern: the glob-style pattern to be matched against
*
* Either/both of text and pattern can be empty strings.
*
* Match text against a glob-style pattern, with wildcards and simple sets:
*
* ? matches any single character.
* * matches any run of characters.
* [xyz] matches a single character from the set: x, y, or z.
* [a-d] matches a single character from the range: a, b, c, or d.
* [a-d0-9] matches a single character from either range.
*
* The special characters ?, [, -, or *, can be matched using a set, eg. [*]
* Behaviour with malformed patterns is undefined, though generally reasonable.
*
* Example patterns: "SD1?", "SD1[0-5]", "*R0", SD*1?[012]*xx"
*
* This function uses one level of recursion per '*' in pattern.
* Since it calls _nothing_ else, and has _no_ explicit local variables,
* this will not cause stack problems for any reasonable use here.
*
* RETURNS:
* 0 on match, 1 otherwise.
*/
static int glob_match (const char *text, const char *pattern)
{
const char *p;
int len;
do {
/* Match single character or a '?' wildcard */
if (*text == *pattern || *pattern == '?') {
if (!*pattern++)
return 0; /* End of both strings: match */
} else {
/* Match single char against a '[' bracketed ']' pattern set */
if (!*text || *pattern != '[')
break; /* Not a pattern set */
while (*++pattern && *pattern != ']' && *text != *pattern) {
if (*pattern == '-' && *(pattern - 1) != '[')
if (*text > *(pattern - 1) && *text < *(pattern + 1)) {
++pattern;
break;
}
}
if (!*pattern || *pattern == ']')
return 1; /* No match */
while (*pattern && *pattern++ != ']');
}
} while (*++text && *pattern);
/*
* check for trailing wildcard: *\0
*/
p = strchr(patt, wildchar);
if (p && ((*(p + 1)) == 0))
len = p - patt;
else {
len = strlen(name);
if (!len) {
if (!*patt)
return 0;
return -1;
/* Match any run of chars against a '*' wildcard */
if (*pattern == '*') {
if (!*++pattern)
return 0; /* Match: avoid recursion at end of pattern */
/* Loop to handle additional pattern chars after the wildcard */
while (*text) {
if (glob_match(text, pattern) == 0)
return 0; /* Remainder matched */
++text; /* Absorb (match) this char and try again */
}
}
return strncmp(patt, name, len);
if (!*text && !*pattern)
return 0; /* End of both strings: match */
return 1; /* No match */
}
static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
{
unsigned char model_num[ATA_ID_PROD_LEN + 1];
@ -4359,10 +4342,10 @@ static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
ata_id_c_string(dev->id, model_rev, ATA_ID_FW_REV, sizeof(model_rev));
while (ad->model_num) {
if (!strn_pattern_cmp(ad->model_num, model_num, '*')) {
if (!glob_match(model_num, ad->model_num)) {
if (ad->model_rev == NULL)
return ad->horkage;
if (!strn_pattern_cmp(ad->model_rev, model_rev, '*'))
if (!glob_match(model_rev, ad->model_rev))
return ad->horkage;
}
ad++;

1
drivers/ata/libata-eh.c
View File

@ -2214,6 +2214,7 @@ const char *ata_get_cmd_descript(u8 command)
{ ATA_CMD_SMART, "SMART" },
{ ATA_CMD_MEDIA_LOCK, "DOOR LOCK" },
{ ATA_CMD_MEDIA_UNLOCK, "DOOR UNLOCK" },
{ ATA_CMD_DSM, "DATA SET MANAGEMENT" },
{ ATA_CMD_CHK_MED_CRD_TYP, "CHECK MEDIA CARD TYPE" },
{ ATA_CMD_CFA_REQ_EXT_ERR, "CFA REQUEST EXTENDED ERROR" },
{ ATA_CMD_CFA_WRITE_NE, "CFA WRITE SECTORS WITHOUT ERASE" },

683
drivers/ata/pata_samsung_cf.c Normal file
View File

@ -0,0 +1,683 @@
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* PATA driver for Samsung SoCs.
* Supports CF Interface in True IDE mode. Currently only PIO mode has been
* implemented; UDMA support has to be added.
*
* Based on:
* PATA driver for AT91SAM9260 Static Memory Controller
* PATA driver for Toshiba SCC controller
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/libata.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <plat/ata.h>
#include <plat/regs-ata.h>
#define DRV_NAME "pata_samsung_cf"
#define DRV_VERSION "0.1"
enum s3c_cpu_type {
TYPE_S3C64XX,
TYPE_S5PC100,
TYPE_S5PV210,
};
/*
* struct s3c_ide_info - S3C PATA instance.
* @clk: The clock resource for this controller.
* @ide_addr: The area mapped for the hardware registers.
* @sfr_addr: The area mapped for the special function registers.
* @irq: The IRQ number we are using.
* @cpu_type: The exact type of this controller.
* @fifo_status_reg: The ATA_FIFO_STATUS register offset.
*/
struct s3c_ide_info {
struct clk *clk;
void __iomem *ide_addr;
void __iomem *sfr_addr;
unsigned int irq;
enum s3c_cpu_type cpu_type;
unsigned int fifo_status_reg;
};
static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
{
u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
}
static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
{
/* Select true-ide as the internal operating mode */
writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
s3c_ide_sfrbase + S3C_CFATA_MUX);
}
static unsigned long
pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
{
int t1 = ata->setup;
int t2 = ata->act8b;
int t2i = ata->rec8b;
ulong piotime;
piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
return piotime;
}
static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct s3c_ide_info *info = ap->host->private_data;
struct ata_timing timing;
int cycle_time;
ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
ulong piotime;
/* Enables IORDY if mode requires it */
if (ata_pio_need_iordy(adev))
ata_cfg |= S3C_ATA_CFG_IORDYEN;
else
ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
ata_timing_compute(adev, adev->pio_mode, &timing,
cycle_time * 1000, 0);
piotime = pata_s3c_setup_timing(info, &timing);
writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
}
/*
* Waits until the IDE controller is able to perform next read/write
* operation to the disk. Needed for 64XX series boards only.
*/
static int wait_for_host_ready(struct s3c_ide_info *info)
{
ulong timeout;
void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
/* wait for maximum of 20 msec */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
if ((readl(fifo_reg) >> 28) == 0)
return 0;
}
return -EBUSY;
}
/*
* Writes to one of the task file registers.
*/
static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
{
struct s3c_ide_info *info = host->private_data;
wait_for_host_ready(info);
writeb(addr, reg);
}
/*
* Reads from one of the task file registers.
*/
static u8 ata_inb(struct ata_host *host, void __iomem *reg)
{
struct s3c_ide_info *info = host->private_data;
u8 temp;
wait_for_host_ready(info);
(void) readb(reg);
wait_for_host_ready(info);
temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
return temp;
}
/*
* pata_s3c_tf_load - send taskfile registers to host controller
*/
static void pata_s3c_tf_load(struct ata_port *ap,
const struct ata_taskfile *tf)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
if (tf->ctl != ap->last_ctl) {
ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
ap->last_ctl = tf->ctl;
ata_wait_idle(ap);
}
if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
}
if (is_addr) {
ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
}
if (tf->flags & ATA_TFLAG_DEVICE)
ata_outb(ap->host, tf->device, ioaddr->device_addr);
ata_wait_idle(ap);
}
/*
* pata_s3c_tf_read - input device's ATA taskfile shadow registers
*/
static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
tf->feature = ata_inb(ap->host, ioaddr->error_addr);
tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
tf->device = ata_inb(ap->host, ioaddr->device_addr);
if (tf->flags & ATA_TFLAG_LBA48) {
ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
ap->last_ctl = tf->ctl;
}
}
/*
* pata_s3c_exec_command - issue ATA command to host controller
*/
static void pata_s3c_exec_command(struct ata_port *ap,
const struct ata_taskfile *tf)
{
ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
ata_sff_pause(ap);
}
/*
* pata_s3c_check_status - Read device status register
*/
static u8 pata_s3c_check_status(struct ata_port *ap)
{
return ata_inb(ap->host, ap->ioaddr.status_addr);
}
/*
* pata_s3c_check_altstatus - Read alternate device status register
*/
static u8 pata_s3c_check_altstatus(struct ata_port *ap)
{
return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
}
/*
* pata_s3c_data_xfer - Transfer data by PIO
*/
unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
unsigned int buflen, int rw)
{
struct ata_port *ap = dev->link->ap;
struct s3c_ide_info *info = ap->host->private_data;
void __iomem *data_addr = ap->ioaddr.data_addr;
unsigned int words = buflen >> 1, i;
u16 *data_ptr = (u16 *)buf;
/* Requires wait same as in ata_inb/ata_outb */
if (rw == READ)
for (i = 0; i < words; i++, data_ptr++) {
wait_for_host_ready(info);
(void) readw(data_addr);
wait_for_host_ready(info);
*data_ptr = readw(info->ide_addr
+ S3C_ATA_PIO_RDATA);
}
else
for (i = 0; i < words; i++, data_ptr++) {
wait_for_host_ready(info);
writew(*data_ptr, data_addr);
}
if (buflen & 0x01)
dev_err(ap->dev, "unexpected trailing data\n");
return words << 1;
}
/*
* pata_s3c_dev_select - Select device on ATA bus
*/
static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
{
u8 tmp = ATA_DEVICE_OBS;
if (device != 0)
tmp |= ATA_DEV1;
ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
ata_sff_pause(ap);
}
/*
* pata_s3c_devchk - PATA device presence detection
*/
static unsigned int pata_s3c_devchk(struct ata_port *ap,
unsigned int device)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
u8 nsect, lbal;
pata_s3c_dev_select(ap, device);
ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
nsect = ata_inb(ap->host, ioaddr->nsect_addr);
lbal = ata_inb(ap->host, ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
return 0; /* nothing found */
}
/*
* pata_s3c_wait_after_reset - wait for devices to become ready after reset
*/
static int pata_s3c_wait_after_reset(struct ata_link *link,
unsigned long deadline)
{
int rc;
msleep(ATA_WAIT_AFTER_RESET);
/* always check readiness of the master device */
rc = ata_sff_wait_ready(link, deadline);
/* -ENODEV means the odd clown forgot the D7 pulldown resistor
* and TF status is 0xff, bail out on it too.
*/
if (rc)
return rc;
return 0;
}
/*
* pata_s3c_bus_softreset - PATA device software reset
*/
static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
unsigned long deadline)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
/* software reset. causes dev0 to be selected */
ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
udelay(20);
ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
udelay(20);
ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
ap->last_ctl = ap->ctl;
return pata_s3c_wait_after_reset(&ap->link, deadline);
}
/*
* pata_s3c_softreset - reset host port via ATA SRST
*/
static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
unsigned long deadline)
{
struct ata_port *ap = link->ap;
unsigned int devmask = 0;
int rc;
u8 err;
/* determine if device 0 is present */
if (pata_s3c_devchk(ap, 0))
devmask |= (1 << 0);
/* select device 0 again */
pata_s3c_dev_select(ap, 0);
/* issue bus reset */
rc = pata_s3c_bus_softreset(ap, deadline);
/* if link is occupied, -ENODEV too is an error */
if (rc && rc != -ENODEV) {
ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
return rc;
}
/* determine by signature whether we have ATA or ATAPI devices */
classes[0] = ata_sff_dev_classify(&ap->link.device[0],
devmask & (1 << 0), &err);
return 0;
}
/*
* pata_s3c_set_devctl - Write device control register
*/
static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
{
ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
}
static struct scsi_host_template pata_s3c_sht = {
ATA_PIO_SHT(DRV_NAME),
};
static struct ata_port_operations pata_s3c_port_ops = {
.inherits = &ata_sff_port_ops,
.sff_check_status = pata_s3c_check_status,
.sff_check_altstatus = pata_s3c_check_altstatus,
.sff_tf_load = pata_s3c_tf_load,
.sff_tf_read = pata_s3c_tf_read,
.sff_data_xfer = pata_s3c_data_xfer,
.sff_exec_command = pata_s3c_exec_command,
.sff_dev_select = pata_s3c_dev_select,
.sff_set_devctl = pata_s3c_set_devctl,
.softreset = pata_s3c_softreset,
.set_piomode = pata_s3c_set_piomode,
};
static struct ata_port_operations pata_s5p_port_ops = {
.inherits = &ata_sff_port_ops,
.set_piomode = pata_s3c_set_piomode,
};
static void pata_s3c_enable(void *s3c_ide_regbase, bool state)
{
u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
temp = state ? (temp | 1) : (temp & ~1);
writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
}
static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
{
struct ata_host *host = dev_instance;
struct s3c_ide_info *info = host->private_data;
u32 reg;
reg = readl(info->ide_addr + S3C_ATA_IRQ);
writel(reg, info->ide_addr + S3C_ATA_IRQ);
return ata_sff_interrupt(irq, dev_instance);
}
static void pata_s3c_hwinit(struct s3c_ide_info *info,
struct s3c_ide_platdata *pdata)
{
switch (info->cpu_type) {
case TYPE_S3C64XX:
/* Configure as big endian */
pata_s3c_cfg_mode(info->sfr_addr);
pata_s3c_set_endian(info->ide_addr, 1);
pata_s3c_enable(info->ide_addr, true);
msleep(100);
/* Remove IRQ Status */
writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
break;
case TYPE_S5PC100:
pata_s3c_cfg_mode(info->sfr_addr);
/* FALLTHROUGH */
case TYPE_S5PV210:
/* Configure as little endian */
pata_s3c_set_endian(info->ide_addr, 0);
pata_s3c_enable(info->ide_addr, true);
msleep(100);
/* Remove IRQ Status */
writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
break;
default:
BUG();
}
}
static int __init pata_s3c_probe(struct platform_device *pdev)
{
struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
struct device *dev = &pdev->dev;
struct s3c_ide_info *info;
struct resource *res;
struct ata_port *ap;
struct ata_host *host;
enum s3c_cpu_type cpu_type;
int ret;
cpu_type = platform_get_device_id(pdev)->driver_data;
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info) {
dev_err(dev, "failed to allocate memory for device data\n");
return -ENOMEM;
}
info->irq = platform_get_irq(pdev, 0);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(dev, "failed to get mem resource\n");
return -EINVAL;
}
if (!devm_request_mem_region(dev, res->start,
resource_size(res), DRV_NAME)) {
dev_err(dev, "error requesting register region\n");
return -EBUSY;
}
info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
if (!info->ide_addr) {
dev_err(dev, "failed to map IO base address\n");
return -ENOMEM;
}
info->clk = clk_get(&pdev->dev, "cfcon");
if (IS_ERR(info->clk)) {
dev_err(dev, "failed to get access to cf controller clock\n");
ret = PTR_ERR(info->clk);
info->clk = NULL;
return ret;
}
clk_enable(info->clk);
/* init ata host */
host = ata_host_alloc(dev, 1);
if (!host) {
dev_err(dev, "failed to allocate ide host\n");
ret = -ENOMEM;
goto stop_clk;
}
ap = host->ports[0];
ap->flags |= ATA_FLAG_MMIO;
ap->pio_mask = ATA_PIO4;
if (cpu_type == TYPE_S3C64XX) {
ap->ops = &pata_s3c_port_ops;
info->sfr_addr = info->ide_addr + 0x1800;
info->ide_addr += 0x1900;
info->fifo_status_reg = 0x94;
} else if (cpu_type == TYPE_S5PC100) {
ap->ops = &pata_s5p_port_ops;
info->sfr_addr = info->ide_addr + 0x1800;
info->ide_addr += 0x1900;
info->fifo_status_reg = 0x84;
} else {
ap->ops = &pata_s5p_port_ops;
info->fifo_status_reg = 0x84;
}
info->cpu_type = cpu_type;
if (info->irq <= 0) {
ap->flags |= ATA_FLAG_PIO_POLLING;
info->irq = 0;
ata_port_desc(ap, "no IRQ, using PIO polling\n");
}
ap->ioaddr.cmd_addr = info->ide_addr + S3C_ATA_CMD;
ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
ata_port_desc(ap, "mmio cmd 0x%llx ",
(unsigned long long)res->start);
host->private_data = info;
if (pdata && pdata->setup_gpio)
pdata->setup_gpio();
/* Set endianness and enable the interface */
pata_s3c_hwinit(info, pdata);
platform_set_drvdata(pdev, host);
return ata_host_activate(host, info->irq,
info->irq ? pata_s3c_irq : NULL,
0, &pata_s3c_sht);
stop_clk:
clk_disable(info->clk);
clk_put(info->clk);
return ret;
}
static int __exit pata_s3c_remove(struct platform_device *pdev)
{
struct ata_host *host = platform_get_drvdata(pdev);
struct s3c_ide_info *info = host->private_data;
ata_host_detach(host);
clk_disable(info->clk);
clk_put(info->clk);
return 0;
}
#ifdef CONFIG_PM
static int pata_s3c_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct ata_host *host = platform_get_drvdata(pdev);
return ata_host_suspend(host, PMSG_SUSPEND);
}
static int pata_s3c_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct ata_host *host = platform_get_drvdata(pdev);
struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
struct s3c_ide_info *info = host->private_data;
pata_s3c_hwinit(info, pdata);
ata_host_resume(host);
return 0;
}
static const struct dev_pm_ops pata_s3c_pm_ops = {
.suspend = pata_s3c_suspend,
.resume = pata_s3c_resume,
};
#endif
/* driver device registration */
static struct platform_device_id pata_s3c_driver_ids[] = {
{
.name = "s3c64xx-pata",
.driver_data = TYPE_S3C64XX,
}, {
.name = "s5pc100-pata",
.driver_data = TYPE_S5PC100,
}, {
.name = "s5pv210-pata",
.driver_data = TYPE_S5PV210,
},
{ }
};
MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
static struct platform_driver pata_s3c_driver = {
.remove = __exit_p(pata_s3c_remove),
.id_table = pata_s3c_driver_ids,
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
#ifdef CONFIG_PM
.pm = &pata_s3c_pm_ops,
#endif
},
};
static int __init pata_s3c_init(void)
{
return platform_driver_probe(&pata_s3c_driver, pata_s3c_probe);
}
static void __exit pata_s3c_exit(void)
{
platform_driver_unregister(&pata_s3c_driver);
}
module_init(pata_s3c_init);
module_exit(pata_s3c_exit);
MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

3
drivers/ata/pata_scc.c
View File

@ -168,8 +168,7 @@ static const unsigned long JCACTSELtbl[2][7] = {
};
static const struct pci_device_id scc_pci_tbl[] = {
{PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
{ } /* terminate list */
};

1756
drivers/ata/sata_dwc_460ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

20
drivers/ata/sata_fsl.c
View File

@ -1096,7 +1096,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
{
struct sata_fsl_host_priv *host_priv = ap->host->private_data;
void __iomem *hcr_base = host_priv->hcr_base;
u32 hstatus, qc_active = 0;
u32 hstatus, done_mask = 0;
struct ata_queued_cmd *qc;
u32 SError;
@ -1116,28 +1116,28 @@ static void sata_fsl_host_intr(struct ata_port *ap)
}
/* Read command completed register */
qc_active = ioread32(hcr_base + CC);
done_mask = ioread32(hcr_base + CC);
VPRINTK("Status of all queues :\n");
VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
qc_active,
VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
done_mask,
ioread32(hcr_base + CA),
ioread32(hcr_base + CE),
ioread32(hcr_base + CQ),
ap->qc_active);
if (qc_active & ap->qc_active) {
if (done_mask & ap->qc_active) {
int i;
/* clear CC bit, this will also complete the interrupt */
iowrite32(qc_active, hcr_base + CC);
iowrite32(done_mask, hcr_base + CC);
DPRINTK("Status of all queues :\n");
DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
qc_active, ioread32(hcr_base + CA),
DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
done_mask, ioread32(hcr_base + CA),
ioread32(hcr_base + CE));
for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
if (qc_active & (1 << i)) {
if (done_mask & (1 << i)) {
qc = ata_qc_from_tag(ap, i);
if (qc) {
ata_qc_complete(qc);
@ -1164,7 +1164,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
/* Spurious Interrupt!! */
DPRINTK("spurious interrupt!!, CC = 0x%x\n",
ioread32(hcr_base + CC));
iowrite32(qc_active, hcr_base + CC);
iowrite32(done_mask, hcr_base + CC);
return;
}
}

47
drivers/ata/sata_mv.c
View File

@ -2716,34 +2716,35 @@ static void mv_err_intr(struct ata_port *ap)
static void mv_process_crpb_response(struct ata_port *ap,
struct mv_crpb *response, unsigned int tag, int ncq_enabled)
{
u8 ata_status;
u16 edma_status = le16_to_cpu(response->flags);
struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
if (qc) {
u8 ata_status;
u16 edma_status = le16_to_cpu(response->flags);
/*
* edma_status from a response queue entry:
* LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
* MSB is saved ATA status from command completion.
*/
if (!ncq_enabled) {
u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
if (err_cause) {
/*
* Error will be seen/handled by mv_err_intr().
* So do nothing at all here.
*/
return;
}
}
ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
if (!ac_err_mask(ata_status))
ata_qc_complete(qc);
/* else: leave it for mv_err_intr() */
} else {
if (unlikely(!qc)) {
ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
__func__, tag);
return;
}
/*
* edma_status from a response queue entry:
* LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
* MSB is saved ATA status from command completion.
*/
if (!ncq_enabled) {
u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
if (err_cause) {
/*
* Error will be seen/handled by
* mv_err_intr(). So do nothing at all here.
*/
return;
}
}
ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
if (!ac_err_mask(ata_status))
ata_qc_complete(qc);
/* else: leave it for mv_err_intr() */
}
static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)

32
drivers/ata/sata_nv.c
View File

@ -1018,7 +1018,7 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
NV_ADMA_STAT_CPBERR |
NV_ADMA_STAT_CMD_COMPLETE)) {
u32 check_commands = notifier_clears[i];
int pos, error = 0;
int pos, rc;
if (status & NV_ADMA_STAT_CPBERR) {
/* check all active commands */
@ -1030,10 +1030,12 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
}
/* check CPBs for completed commands */
while ((pos = ffs(check_commands)) && !error) {
while ((pos = ffs(check_commands))) {
pos--;
error = nv_adma_check_cpb(ap, pos,
rc = nv_adma_check_cpb(ap, pos,
notifier_error & (1 << pos));
if (unlikely(rc))
check_commands = 0;
check_commands &= ~(1 << pos);
}
}
@ -2129,7 +2131,6 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
struct nv_swncq_port_priv *pp = ap->private_data;
struct ata_eh_info *ehi = &ap->link.eh_info;
u32 sactive;
int nr_done = 0;
u32 done_mask;
int i;
u8 host_stat;
@ -2170,22 +2171,21 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
pp->dhfis_bits &= ~(1 << i);
pp->dmafis_bits &= ~(1 << i);
pp->sdbfis_bits |= (1 << i);
nr_done++;
}
}
if (!ap->qc_active) {
DPRINTK("over\n");
nv_swncq_pp_reinit(ap);
return nr_done;
return 0;
}
if (pp->qc_active & pp->dhfis_bits)
return nr_done;
return 0;
if ((pp->ncq_flags & ncq_saw_backout) ||
(pp->qc_active ^ pp->dhfis_bits))
/* if the controller cann't get a device to host register FIS,
/* if the controller can't get a device to host register FIS,
* The driver needs to reissue the new command.
*/
lack_dhfis = 1;
@ -2202,7 +2202,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
if (lack_dhfis) {
qc = ata_qc_from_tag(ap, pp->last_issue_tag);
nv_swncq_issue_atacmd(ap, qc);
return nr_done;
return 0;
}
if (pp->defer_queue.defer_bits) {
@ -2212,7 +2212,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
nv_swncq_issue_atacmd(ap, qc);
}
return nr_done;
return 0;
}
static inline u32 nv_swncq_tag(struct ata_port *ap)
@ -2224,7 +2224,7 @@ static inline u32 nv_swncq_tag(struct ata_port *ap)
return (tag & 0x1f);
}
static int nv_swncq_dmafis(struct ata_port *ap)
static void nv_swncq_dmafis(struct ata_port *ap)
{
struct ata_queued_cmd *qc;
unsigned int rw;
@ -2239,7 +2239,7 @@ static int nv_swncq_dmafis(struct ata_port *ap)
qc = ata_qc_from_tag(ap, tag);
if (unlikely(!qc))
return 0;
return;
rw = qc->tf.flags & ATA_TFLAG_WRITE;
@ -2254,8 +2254,6 @@ static int nv_swncq_dmafis(struct ata_port *ap)
dmactl |= ATA_DMA_WR;
iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
return 1;
}
static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
@ -2265,7 +2263,6 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
struct ata_eh_info *ehi = &ap->link.eh_info;
u32 serror;
u8 ata_stat;
int rc = 0;
ata_stat = ap->ops->sff_check_status(ap);
nv_swncq_irq_clear(ap, fis);
@ -2310,8 +2307,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
"dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
ap->print_id, pp->qc_active, pp->dhfis_bits,
pp->dmafis_bits, readl(pp->sactive_block));
rc = nv_swncq_sdbfis(ap);
if (rc < 0)
if (nv_swncq_sdbfis(ap) < 0)
goto irq_error;
}
@ -2348,7 +2344,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
*/
pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
pp->ncq_flags |= ncq_saw_dmas;
rc = nv_swncq_dmafis(ap);
nv_swncq_dmafis(ap);
}
irq_exit:

6
drivers/pci/quirks.c
View File

@ -1459,6 +1459,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev)
switch (pdev->device) {
case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
/* The controller should be in single function ahci mode */
conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
break;
@ -1470,6 +1471,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev)
/* Fall through */
case PCI_DEVICE_ID_JMICRON_JMB361:
case PCI_DEVICE_ID_JMICRON_JMB363:
case PCI_DEVICE_ID_JMICRON_JMB369:
/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
/* Set the class codes correctly and then direct IDE 0 */
conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
@ -1496,16 +1498,20 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, qui
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
#endif

4
include/linux/ahci_platform.h
View File

@ -15,11 +15,13 @@
#ifndef _AHCI_PLATFORM_H
#define _AHCI_PLATFORM_H
#include <linux/compiler.h>
struct device;
struct ata_port_info;
struct ahci_platform_data {
int (*init)(struct device *dev);
int (*init)(struct device *dev, void __iomem *addr);
void (*exit)(struct device *dev);
const struct ata_port_info *ata_port_info;
unsigned int force_port_map;

2
include/linux/pci_ids.h
View File

@ -2325,9 +2325,11 @@
#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361
#define PCI_DEVICE_ID_JMICRON_JMB362 0x2362
#define PCI_DEVICE_ID_JMICRON_JMB363 0x2363
#define PCI_DEVICE_ID_JMICRON_JMB364 0x2364
#define PCI_DEVICE_ID_JMICRON_JMB365 0x2365
#define PCI_DEVICE_ID_JMICRON_JMB366 0x2366
#define PCI_DEVICE_ID_JMICRON_JMB368 0x2368
#define PCI_DEVICE_ID_JMICRON_JMB369 0x2369
#define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381
#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
#define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383