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Merge tag 'v3.2-rc2' into staging/for_v3.3
* tag 'v3.2-rc2': (3068 commits) Linux 3.2-rc2 hfs: add sanity check for file name length fsl-rio: fix compile error blackfin: Fixup export.h includes Blackfin: add serial TX IRQ in individual platform resource virtio-pci: fix use after free ACPI / cpuidle: Remove acpi_idle_suspend (to fix suspend regression) drm/radeon/kms/combios: fix dynamic allocation of PM clock modes [CPUFREQ] db8500: fix build error due to undeclared i variable bma023: Add SFI translation for this device vrtc: change its year offset from 1960 to 1972 ce4100: fix a build error arm/imx: fix imx6q mmc error when mounting rootfs arm/imx: fix AUTO_ZRELADDR selection arm/imx: fix the references to ARCH_MX3 ARM: mx51/53: set pwm clock parent to ipg_perclk btrfs: rename the option to nospace_cache drm/radeon/kms/pm: switch to dynamically allocating clock mode array drm/radeon/kms: optimize r600_pm_profile_init drm/radeon/kms/pm: add a proper pm profile init function for fusion ... Conflicts: drivers/media/radio/Kconfig
This commit is contained in:
commit
12cbfd0a3c
2
.mailmap
2
.mailmap
@ -68,6 +68,7 @@ Juha Yrjola <juha.yrjola@solidboot.com>
|
||||
Kay Sievers <kay.sievers@vrfy.org>
|
||||
Kenneth W Chen <kenneth.w.chen@intel.com>
|
||||
Koushik <raghavendra.koushik@neterion.com>
|
||||
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
Linas Vepstas <linas@austin.ibm.com>
|
||||
Mark Brown <broonie@sirena.org.uk>
|
||||
@ -111,3 +112,4 @@ Uwe Kleine-König <ukl@pengutronix.de>
|
||||
Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
|
||||
Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
|
||||
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
|
||||
Yusuke Goda <goda.yusuke@renesas.com>
|
||||
|
22
Documentation/ABI/stable/sysfs-acpi-pmprofile
Normal file
22
Documentation/ABI/stable/sysfs-acpi-pmprofile
Normal file
@ -0,0 +1,22 @@
|
||||
What: /sys/firmware/acpi/pm_profile
|
||||
Date: 03-Nov-2011
|
||||
KernelVersion: v3.2
|
||||
Contact: linux-acpi@vger.kernel.org
|
||||
Description: The ACPI pm_profile sysfs interface exports the platform
|
||||
power management (and performance) requirement expectations
|
||||
as provided by BIOS. The integer value is directly passed as
|
||||
retrieved from the FADT ACPI table.
|
||||
Values: For possible values see ACPI specification:
|
||||
5.2.9 Fixed ACPI Description Table (FADT)
|
||||
Field: Preferred_PM_Profile
|
||||
|
||||
Currently these values are defined by spec:
|
||||
0 Unspecified
|
||||
1 Desktop
|
||||
2 Mobile
|
||||
3 Workstation
|
||||
4 Enterprise Server
|
||||
5 SOHO Server
|
||||
6 Appliance PC
|
||||
7 Performance Server
|
||||
>7 Reserved
|
19
Documentation/ABI/testing/debugfs-ideapad
Normal file
19
Documentation/ABI/testing/debugfs-ideapad
Normal file
@ -0,0 +1,19 @@
|
||||
What: /sys/kernel/debug/ideapad/cfg
|
||||
Date: Sep 2011
|
||||
KernelVersion: 3.2
|
||||
Contact: Ike Panhc <ike.pan@canonical.com>
|
||||
Description:
|
||||
|
||||
cfg shows the return value of _CFG method in VPC2004 device. It tells machine
|
||||
capability and what graphic component within the machine.
|
||||
|
||||
|
||||
What: /sys/kernel/debug/ideapad/status
|
||||
Date: Sep 2011
|
||||
KernelVersion: 3.2
|
||||
Contact: Ike Panhc <ike.pan@canonical.com>
|
||||
Description:
|
||||
|
||||
status shows infos we can read and tells its meaning and value.
|
||||
|
||||
|
@ -71,3 +71,10 @@ Description: Value of 1 indicates the controller can honor the reset_devices
|
||||
a dump device, as kdump requires resetting the device in order
|
||||
to work reliably.
|
||||
|
||||
Where: /sys/bus/pci/devices/<dev>/ccissX/transport_mode
|
||||
Date: July 2011
|
||||
Kernel Version: 3.0
|
||||
Contact: iss_storagedev@hp.com
|
||||
Description: Value of "simple" indicates that the controller has been placed
|
||||
in "simple mode". Value of "performant" indicates that the
|
||||
controller has been placed in "performant mode".
|
||||
|
@ -5,19 +5,4 @@ Contact: "Ike Panhc <ike.pan@canonical.com>"
|
||||
Description:
|
||||
Control the power of camera module. 1 means on, 0 means off.
|
||||
|
||||
What: /sys/devices/platform/ideapad/cfg
|
||||
Date: Jun 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: "Ike Panhc <ike.pan@canonical.com>"
|
||||
Description:
|
||||
Ideapad capability bits.
|
||||
Bit 8-10: 1 - Intel graphic only
|
||||
2 - ATI graphic only
|
||||
3 - Nvidia graphic only
|
||||
4 - Intel and ATI graphic
|
||||
5 - Intel and Nvidia graphic
|
||||
Bit 16: Bluetooth exist (1 for exist)
|
||||
Bit 17: 3G exist (1 for exist)
|
||||
Bit 18: Wifi exist (1 for exist)
|
||||
Bit 19: Camera exist (1 for exist)
|
||||
|
||||
|
@ -166,8 +166,8 @@ if (condition)
|
||||
else
|
||||
do_that();
|
||||
|
||||
This does not apply if one branch of a conditional statement is a single
|
||||
statement. Use braces in both branches.
|
||||
This does not apply if only one branch of a conditional statement is a single
|
||||
statement; in the latter case use braces in both branches:
|
||||
|
||||
if (condition) {
|
||||
do_this();
|
||||
|
@ -50,6 +50,13 @@ specify the GFP_ flags (see kmalloc) for the allocation (the
|
||||
implementation may choose to ignore flags that affect the location of
|
||||
the returned memory, like GFP_DMA).
|
||||
|
||||
void *
|
||||
dma_zalloc_coherent(struct device *dev, size_t size,
|
||||
dma_addr_t *dma_handle, gfp_t flag)
|
||||
|
||||
Wraps dma_alloc_coherent() and also zeroes the returned memory if the
|
||||
allocation attempt succeeded.
|
||||
|
||||
void
|
||||
dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
|
||||
dma_addr_t dma_handle)
|
||||
|
@ -32,7 +32,7 @@
|
||||
The Linux DRM layer contains code intended to support the needs
|
||||
of complex graphics devices, usually containing programmable
|
||||
pipelines well suited to 3D graphics acceleration. Graphics
|
||||
drivers in the kernel can make use of DRM functions to make
|
||||
drivers in the kernel may make use of DRM functions to make
|
||||
tasks like memory management, interrupt handling and DMA easier,
|
||||
and provide a uniform interface to applications.
|
||||
</para>
|
||||
@ -57,10 +57,10 @@
|
||||
existing drivers.
|
||||
</para>
|
||||
<para>
|
||||
First, we'll go over some typical driver initialization
|
||||
First, we go over some typical driver initialization
|
||||
requirements, like setting up command buffers, creating an
|
||||
initial output configuration, and initializing core services.
|
||||
Subsequent sections will cover core internals in more detail,
|
||||
Subsequent sections cover core internals in more detail,
|
||||
providing implementation notes and examples.
|
||||
</para>
|
||||
<para>
|
||||
@ -74,7 +74,7 @@
|
||||
</para>
|
||||
<para>
|
||||
The core of every DRM driver is struct drm_driver. Drivers
|
||||
will typically statically initialize a drm_driver structure,
|
||||
typically statically initialize a drm_driver structure,
|
||||
then pass it to drm_init() at load time.
|
||||
</para>
|
||||
|
||||
@ -88,8 +88,8 @@
|
||||
</para>
|
||||
<programlisting>
|
||||
static struct drm_driver driver = {
|
||||
/* don't use mtrr's here, the Xserver or user space app should
|
||||
* deal with them for intel hardware.
|
||||
/* Don't use MTRRs here; the Xserver or userspace app should
|
||||
* deal with them for Intel hardware.
|
||||
*/
|
||||
.driver_features =
|
||||
DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
|
||||
@ -154,8 +154,8 @@
|
||||
</programlisting>
|
||||
<para>
|
||||
In the example above, taken from the i915 DRM driver, the driver
|
||||
sets several flags indicating what core features it supports.
|
||||
We'll go over the individual callbacks in later sections. Since
|
||||
sets several flags indicating what core features it supports;
|
||||
we go over the individual callbacks in later sections. Since
|
||||
flags indicate which features your driver supports to the DRM
|
||||
core, you need to set most of them prior to calling drm_init(). Some,
|
||||
like DRIVER_MODESET can be set later based on user supplied parameters,
|
||||
@ -203,8 +203,8 @@
|
||||
<term>DRIVER_HAVE_IRQ</term><term>DRIVER_IRQ_SHARED</term>
|
||||
<listitem>
|
||||
<para>
|
||||
DRIVER_HAVE_IRQ indicates whether the driver has a IRQ
|
||||
handler, DRIVER_IRQ_SHARED indicates whether the device &
|
||||
DRIVER_HAVE_IRQ indicates whether the driver has an IRQ
|
||||
handler. DRIVER_IRQ_SHARED indicates whether the device &
|
||||
handler support shared IRQs (note that this is required of
|
||||
PCI drivers).
|
||||
</para>
|
||||
@ -214,8 +214,8 @@
|
||||
<term>DRIVER_DMA_QUEUE</term>
|
||||
<listitem>
|
||||
<para>
|
||||
If the driver queues DMA requests and completes them
|
||||
asynchronously, this flag should be set. Deprecated.
|
||||
Should be set if the driver queues DMA requests and completes them
|
||||
asynchronously. Deprecated.
|
||||
</para>
|
||||
</listitem>
|
||||
</varlistentry>
|
||||
@ -238,7 +238,7 @@
|
||||
</variablelist>
|
||||
<para>
|
||||
In this specific case, the driver requires AGP and supports
|
||||
IRQs. DMA, as we'll see, is handled by device specific ioctls
|
||||
IRQs. DMA, as discussed later, is handled by device-specific ioctls
|
||||
in this case. It also supports the kernel mode setting APIs, though
|
||||
unlike in the actual i915 driver source, this example unconditionally
|
||||
exports KMS capability.
|
||||
@ -269,36 +269,34 @@
|
||||
initial output configuration.
|
||||
</para>
|
||||
<para>
|
||||
Note that the tasks performed at driver load time must not
|
||||
conflict with DRM client requirements. For instance, if user
|
||||
If compatibility is a concern (e.g. with drivers converted over
|
||||
to the new interfaces from the old ones), care must be taken to
|
||||
prevent device initialization and control that is incompatible with
|
||||
currently active userspace drivers. For instance, if user
|
||||
level mode setting drivers are in use, it would be problematic
|
||||
to perform output discovery & configuration at load time.
|
||||
Likewise, if pre-memory management aware user level drivers are
|
||||
Likewise, if user-level drivers unaware of memory management are
|
||||
in use, memory management and command buffer setup may need to
|
||||
be omitted. These requirements are driver specific, and care
|
||||
be omitted. These requirements are driver-specific, and care
|
||||
needs to be taken to keep both old and new applications and
|
||||
libraries working. The i915 driver supports the "modeset"
|
||||
module parameter to control whether advanced features are
|
||||
enabled at load time or in legacy fashion. If compatibility is
|
||||
a concern (e.g. with drivers converted over to the new interfaces
|
||||
from the old ones), care must be taken to prevent incompatible
|
||||
device initialization and control with the currently active
|
||||
userspace drivers.
|
||||
enabled at load time or in legacy fashion.
|
||||
</para>
|
||||
|
||||
<sect2>
|
||||
<title>Driver private & performance counters</title>
|
||||
<para>
|
||||
The driver private hangs off the main drm_device structure and
|
||||
can be used for tracking various device specific bits of
|
||||
can be used for tracking various device-specific bits of
|
||||
information, like register offsets, command buffer status,
|
||||
register state for suspend/resume, etc. At load time, a
|
||||
driver can simply allocate one and set drm_device.dev_priv
|
||||
appropriately; at unload the driver can free it and set
|
||||
drm_device.dev_priv to NULL.
|
||||
driver may simply allocate one and set drm_device.dev_priv
|
||||
appropriately; it should be freed and drm_device.dev_priv set
|
||||
to NULL when the driver is unloaded.
|
||||
</para>
|
||||
<para>
|
||||
The DRM supports several counters which can be used for rough
|
||||
The DRM supports several counters which may be used for rough
|
||||
performance characterization. Note that the DRM stat counter
|
||||
system is not often used by applications, and supporting
|
||||
additional counters is completely optional.
|
||||
@ -307,15 +305,15 @@
|
||||
These interfaces are deprecated and should not be used. If performance
|
||||
monitoring is desired, the developer should investigate and
|
||||
potentially enhance the kernel perf and tracing infrastructure to export
|
||||
GPU related performance information to performance monitoring
|
||||
tools and applications.
|
||||
GPU related performance information for consumption by performance
|
||||
monitoring tools and applications.
|
||||
</para>
|
||||
</sect2>
|
||||
|
||||
<sect2>
|
||||
<title>Configuring the device</title>
|
||||
<para>
|
||||
Obviously, device configuration will be device specific.
|
||||
Obviously, device configuration is device-specific.
|
||||
However, there are several common operations: finding a
|
||||
device's PCI resources, mapping them, and potentially setting
|
||||
up an IRQ handler.
|
||||
@ -323,10 +321,10 @@
|
||||
<para>
|
||||
Finding & mapping resources is fairly straightforward. The
|
||||
DRM wrapper functions, drm_get_resource_start() and
|
||||
drm_get_resource_len() can be used to find BARs on the given
|
||||
drm_get_resource_len(), may be used to find BARs on the given
|
||||
drm_device struct. Once those values have been retrieved, the
|
||||
driver load function can call drm_addmap() to create a new
|
||||
mapping for the BAR in question. Note you'll probably want a
|
||||
mapping for the BAR in question. Note that you probably want a
|
||||
drm_local_map_t in your driver private structure to track any
|
||||
mappings you create.
|
||||
<!-- !Fdrivers/gpu/drm/drm_bufs.c drm_get_resource_* -->
|
||||
@ -335,20 +333,20 @@
|
||||
<para>
|
||||
if compatibility with other operating systems isn't a concern
|
||||
(DRM drivers can run under various BSD variants and OpenSolaris),
|
||||
native Linux calls can be used for the above, e.g. pci_resource_*
|
||||
native Linux calls may be used for the above, e.g. pci_resource_*
|
||||
and iomap*/iounmap. See the Linux device driver book for more
|
||||
info.
|
||||
</para>
|
||||
<para>
|
||||
Once you have a register map, you can use the DRM_READn() and
|
||||
Once you have a register map, you may use the DRM_READn() and
|
||||
DRM_WRITEn() macros to access the registers on your device, or
|
||||
use driver specific versions to offset into your MMIO space
|
||||
relative to a driver specific base pointer (see I915_READ for
|
||||
example).
|
||||
use driver-specific versions to offset into your MMIO space
|
||||
relative to a driver-specific base pointer (see I915_READ for
|
||||
an example).
|
||||
</para>
|
||||
<para>
|
||||
If your device supports interrupt generation, you may want to
|
||||
setup an interrupt handler at driver load time as well. This
|
||||
set up an interrupt handler when the driver is loaded. This
|
||||
is done using the drm_irq_install() function. If your device
|
||||
supports vertical blank interrupts, it should call
|
||||
drm_vblank_init() to initialize the core vblank handling code before
|
||||
@ -357,7 +355,7 @@
|
||||
</para>
|
||||
<!--!Fdrivers/char/drm/drm_irq.c drm_irq_install-->
|
||||
<para>
|
||||
Once your interrupt handler is registered (it'll use your
|
||||
Once your interrupt handler is registered (it uses your
|
||||
drm_driver.irq_handler as the actual interrupt handling
|
||||
function), you can safely enable interrupts on your device,
|
||||
assuming any other state your interrupt handler uses is also
|
||||
@ -371,10 +369,10 @@
|
||||
using the pci_map_rom() call, a convenience function that
|
||||
takes care of mapping the actual ROM, whether it has been
|
||||
shadowed into memory (typically at address 0xc0000) or exists
|
||||
on the PCI device in the ROM BAR. Note that once you've
|
||||
mapped the ROM and extracted any necessary information, be
|
||||
sure to unmap it; on many devices the ROM address decoder is
|
||||
shared with other BARs, so leaving it mapped can cause
|
||||
on the PCI device in the ROM BAR. Note that after the ROM
|
||||
has been mapped and any necessary information has been extracted,
|
||||
it should be unmapped; on many devices, the ROM address decoder is
|
||||
shared with other BARs, so leaving it mapped could cause
|
||||
undesired behavior like hangs or memory corruption.
|
||||
<!--!Fdrivers/pci/rom.c pci_map_rom-->
|
||||
</para>
|
||||
@ -389,9 +387,9 @@
|
||||
should support a memory manager.
|
||||
</para>
|
||||
<para>
|
||||
If your driver supports memory management (it should!), you'll
|
||||
If your driver supports memory management (it should!), you
|
||||
need to set that up at load time as well. How you initialize
|
||||
it depends on which memory manager you're using, TTM or GEM.
|
||||
it depends on which memory manager you're using: TTM or GEM.
|
||||
</para>
|
||||
<sect3>
|
||||
<title>TTM initialization</title>
|
||||
@ -401,7 +399,7 @@
|
||||
and devices with dedicated video RAM (VRAM), i.e. most discrete
|
||||
graphics devices. If your device has dedicated RAM, supporting
|
||||
TTM is desirable. TTM also integrates tightly with your
|
||||
driver specific buffer execution function. See the radeon
|
||||
driver-specific buffer execution function. See the radeon
|
||||
driver for examples.
|
||||
</para>
|
||||
<para>
|
||||
@ -429,21 +427,21 @@
|
||||
created by the memory manager at runtime. Your global TTM should
|
||||
have a type of TTM_GLOBAL_TTM_MEM. The size field for the global
|
||||
object should be sizeof(struct ttm_mem_global), and the init and
|
||||
release hooks should point at your driver specific init and
|
||||
release routines, which will probably eventually call
|
||||
ttm_mem_global_init and ttm_mem_global_release respectively.
|
||||
release hooks should point at your driver-specific init and
|
||||
release routines, which probably eventually call
|
||||
ttm_mem_global_init and ttm_mem_global_release, respectively.
|
||||
</para>
|
||||
<para>
|
||||
Once your global TTM accounting structure is set up and initialized
|
||||
(done by calling ttm_global_item_ref on the global object you
|
||||
just created), you'll need to create a buffer object TTM to
|
||||
by calling ttm_global_item_ref() on it,
|
||||
you need to create a buffer object TTM to
|
||||
provide a pool for buffer object allocation by clients and the
|
||||
kernel itself. The type of this object should be TTM_GLOBAL_TTM_BO,
|
||||
and its size should be sizeof(struct ttm_bo_global). Again,
|
||||
driver specific init and release functions can be provided,
|
||||
likely eventually calling ttm_bo_global_init and
|
||||
ttm_bo_global_release, respectively. Also like the previous
|
||||
object, ttm_global_item_ref is used to create an initial reference
|
||||
driver-specific init and release functions may be provided,
|
||||
likely eventually calling ttm_bo_global_init() and
|
||||
ttm_bo_global_release(), respectively. Also, like the previous
|
||||
object, ttm_global_item_ref() is used to create an initial reference
|
||||
count for the TTM, which will call your initialization function.
|
||||
</para>
|
||||
</sect3>
|
||||
@ -453,27 +451,26 @@
|
||||
GEM is an alternative to TTM, designed specifically for UMA
|
||||
devices. It has simpler initialization and execution requirements
|
||||
than TTM, but has no VRAM management capability. Core GEM
|
||||
initialization is comprised of a basic drm_mm_init call to create
|
||||
is initialized by calling drm_mm_init() to create
|
||||
a GTT DRM MM object, which provides an address space pool for
|
||||
object allocation. In a KMS configuration, the driver will
|
||||
need to allocate and initialize a command ring buffer following
|
||||
basic GEM initialization. Most UMA devices have a so-called
|
||||
object allocation. In a KMS configuration, the driver
|
||||
needs to allocate and initialize a command ring buffer following
|
||||
core GEM initialization. A UMA device usually has what is called a
|
||||
"stolen" memory region, which provides space for the initial
|
||||
framebuffer and large, contiguous memory regions required by the
|
||||
device. This space is not typically managed by GEM, and must
|
||||
device. This space is not typically managed by GEM, and it must
|
||||
be initialized separately into its own DRM MM object.
|
||||
</para>
|
||||
<para>
|
||||
Initialization will be driver specific, and will depend on
|
||||
the architecture of the device. In the case of Intel
|
||||
Initialization is driver-specific. In the case of Intel
|
||||
integrated graphics chips like 965GM, GEM initialization can
|
||||
be done by calling the internal GEM init function,
|
||||
i915_gem_do_init(). Since the 965GM is a UMA device
|
||||
(i.e. it doesn't have dedicated VRAM), GEM will manage
|
||||
(i.e. it doesn't have dedicated VRAM), GEM manages
|
||||
making regular RAM available for GPU operations. Memory set
|
||||
aside by the BIOS (called "stolen" memory by the i915
|
||||
driver) will be managed by the DRM memrange allocator; the
|
||||
rest of the aperture will be managed by GEM.
|
||||
driver) is managed by the DRM memrange allocator; the
|
||||
rest of the aperture is managed by GEM.
|
||||
<programlisting>
|
||||
/* Basic memrange allocator for stolen space (aka vram) */
|
||||
drm_memrange_init(&dev_priv->vram, 0, prealloc_size);
|
||||
@ -483,7 +480,7 @@
|
||||
<!--!Edrivers/char/drm/drm_memrange.c-->
|
||||
</para>
|
||||
<para>
|
||||
Once the memory manager has been set up, we can allocate the
|
||||
Once the memory manager has been set up, we may allocate the
|
||||
command buffer. In the i915 case, this is also done with a
|
||||
GEM function, i915_gem_init_ringbuffer().
|
||||
</para>
|
||||
@ -493,16 +490,25 @@
|
||||
<sect2>
|
||||
<title>Output configuration</title>
|
||||
<para>
|
||||
The final initialization task is output configuration. This involves
|
||||
finding and initializing the CRTCs, encoders and connectors
|
||||
for your device, creating an initial configuration and
|
||||
registering a framebuffer console driver.
|
||||
The final initialization task is output configuration. This involves:
|
||||
<itemizedlist>
|
||||
<listitem>
|
||||
Finding and initializing the CRTCs, encoders, and connectors
|
||||
for the device.
|
||||
</listitem>
|
||||
<listitem>
|
||||
Creating an initial configuration.
|
||||
</listitem>
|
||||
<listitem>
|
||||
Registering a framebuffer console driver.
|
||||
</listitem>
|
||||
</itemizedlist>
|
||||
</para>
|
||||
<sect3>
|
||||
<title>Output discovery and initialization</title>
|
||||
<para>
|
||||
Several core functions exist to create CRTCs, encoders and
|
||||
connectors, namely drm_crtc_init(), drm_connector_init() and
|
||||
Several core functions exist to create CRTCs, encoders, and
|
||||
connectors, namely: drm_crtc_init(), drm_connector_init(), and
|
||||
drm_encoder_init(), along with several "helper" functions to
|
||||
perform common tasks.
|
||||
</para>
|
||||
@ -555,10 +561,10 @@ void intel_crt_init(struct drm_device *dev)
|
||||
</programlisting>
|
||||
<para>
|
||||
In the example above (again, taken from the i915 driver), a
|
||||
CRT connector and encoder combination is created. A device
|
||||
specific i2c bus is also created, for fetching EDID data and
|
||||
CRT connector and encoder combination is created. A device-specific
|
||||
i2c bus is also created for fetching EDID data and
|
||||
performing monitor detection. Once the process is complete,
|
||||
the new connector is registered with sysfs, to make its
|
||||
the new connector is registered with sysfs to make its
|
||||
properties available to applications.
|
||||
</para>
|
||||
<sect4>
|
||||
@ -567,12 +573,12 @@ void intel_crt_init(struct drm_device *dev)
|
||||
Since many PC-class graphics devices have similar display output
|
||||
designs, the DRM provides a set of helper functions to make
|
||||
output management easier. The core helper routines handle
|
||||
encoder re-routing and disabling of unused functions following
|
||||
mode set. Using the helpers is optional, but recommended for
|
||||
encoder re-routing and the disabling of unused functions following
|
||||
mode setting. Using the helpers is optional, but recommended for
|
||||
devices with PC-style architectures (i.e. a set of display planes
|
||||
for feeding pixels to encoders which are in turn routed to
|
||||
connectors). Devices with more complex requirements needing
|
||||
finer grained management can opt to use the core callbacks
|
||||
finer grained management may opt to use the core callbacks
|
||||
directly.
|
||||
</para>
|
||||
<para>
|
||||
@ -580,17 +586,25 @@ void intel_crt_init(struct drm_device *dev)
|
||||
</para>
|
||||
</sect4>
|
||||
<para>
|
||||
For each encoder, CRTC and connector, several functions must
|
||||
be provided, depending on the object type. Encoder objects
|
||||
need to provide a DPMS (basically on/off) function, mode fixup
|
||||
(for converting requested modes into native hardware timings),
|
||||
and prepare, set and commit functions for use by the core DRM
|
||||
helper functions. Connector helpers need to provide mode fetch and
|
||||
validity functions as well as an encoder matching function for
|
||||
returning an ideal encoder for a given connector. The core
|
||||
connector functions include a DPMS callback, (deprecated)
|
||||
save/restore routines, detection, mode probing, property handling,
|
||||
and cleanup functions.
|
||||
Each encoder object needs to provide:
|
||||
<itemizedlist>
|
||||
<listitem>
|
||||
A DPMS (basically on/off) function.
|
||||
</listitem>
|
||||
<listitem>
|
||||
A mode-fixup function (for converting requested modes into
|
||||
native hardware timings).
|
||||
</listitem>
|
||||
<listitem>
|
||||
Functions (prepare, set, and commit) for use by the core DRM
|
||||
helper functions.
|
||||
</listitem>
|
||||
</itemizedlist>
|
||||
Connector helpers need to provide functions (mode-fetch, validity,
|
||||
and encoder-matching) for returning an ideal encoder for a given
|
||||
connector. The core connector functions include a DPMS callback,
|
||||
save/restore routines (deprecated), detection, mode probing,
|
||||
property handling, and cleanup functions.
|
||||
</para>
|
||||
<!--!Edrivers/char/drm/drm_crtc.h-->
|
||||
<!--!Edrivers/char/drm/drm_crtc.c-->
|
||||
@ -605,22 +619,33 @@ void intel_crt_init(struct drm_device *dev)
|
||||
<title>VBlank event handling</title>
|
||||
<para>
|
||||
The DRM core exposes two vertical blank related ioctls:
|
||||
DRM_IOCTL_WAIT_VBLANK and DRM_IOCTL_MODESET_CTL.
|
||||
<variablelist>
|
||||
<varlistentry>
|
||||
<term>DRM_IOCTL_WAIT_VBLANK</term>
|
||||
<listitem>
|
||||
<para>
|
||||
This takes a struct drm_wait_vblank structure as its argument,
|
||||
and it is used to block or request a signal when a specified
|
||||
vblank event occurs.
|
||||
</para>
|
||||
</listitem>
|
||||
</varlistentry>
|
||||
<varlistentry>
|
||||
<term>DRM_IOCTL_MODESET_CTL</term>
|
||||
<listitem>
|
||||
<para>
|
||||
This should be called by application level drivers before and
|
||||
after mode setting, since on many devices the vertical blank
|
||||
counter is reset at that time. Internally, the DRM snapshots
|
||||
the last vblank count when the ioctl is called with the
|
||||
_DRM_PRE_MODESET command, so that the counter won't go backwards
|
||||
(which is dealt with when _DRM_POST_MODESET is used).
|
||||
</para>
|
||||
</listitem>
|
||||
</varlistentry>
|
||||
</variablelist>
|
||||
<!--!Edrivers/char/drm/drm_irq.c-->
|
||||
</para>
|
||||
<para>
|
||||
DRM_IOCTL_WAIT_VBLANK takes a struct drm_wait_vblank structure
|
||||
as its argument, and is used to block or request a signal when a
|
||||
specified vblank event occurs.
|
||||
</para>
|
||||
<para>
|
||||
DRM_IOCTL_MODESET_CTL should be called by application level
|
||||
drivers before and after mode setting, since on many devices the
|
||||
vertical blank counter will be reset at that time. Internally,
|
||||
the DRM snapshots the last vblank count when the ioctl is called
|
||||
with the _DRM_PRE_MODESET command so that the counter won't go
|
||||
backwards (which is dealt with when _DRM_POST_MODESET is used).
|
||||
</para>
|
||||
<para>
|
||||
To support the functions above, the DRM core provides several
|
||||
helper functions for tracking vertical blank counters, and
|
||||
@ -632,24 +657,24 @@ void intel_crt_init(struct drm_device *dev)
|
||||
register. The enable and disable vblank callbacks should enable
|
||||
and disable vertical blank interrupts, respectively. In the
|
||||
absence of DRM clients waiting on vblank events, the core DRM
|
||||
code will use the disable_vblank() function to disable
|
||||
interrupts, which saves power. They'll be re-enabled again when
|
||||
code uses the disable_vblank() function to disable
|
||||
interrupts, which saves power. They are re-enabled again when
|
||||
a client calls the vblank wait ioctl above.
|
||||
</para>
|
||||
<para>
|
||||
Devices that don't provide a count register can simply use an
|
||||
A device that doesn't provide a count register may simply use an
|
||||
internal atomic counter incremented on every vertical blank
|
||||
interrupt, and can make their enable and disable vblank
|
||||
functions into no-ops.
|
||||
interrupt (and then treat the enable_vblank() and disable_vblank()
|
||||
callbacks as no-ops).
|
||||
</para>
|
||||
</sect1>
|
||||
|
||||
<sect1>
|
||||
<title>Memory management</title>
|
||||
<para>
|
||||
The memory manager lies at the heart of many DRM operations, and
|
||||
is also required to support advanced client features like OpenGL
|
||||
pbuffers. The DRM currently contains two memory managers, TTM
|
||||
The memory manager lies at the heart of many DRM operations; it
|
||||
is required to support advanced client features like OpenGL
|
||||
pbuffers. The DRM currently contains two memory managers: TTM
|
||||
and GEM.
|
||||
</para>
|
||||
|
||||
@ -679,41 +704,46 @@ void intel_crt_init(struct drm_device *dev)
|
||||
<para>
|
||||
GEM-enabled drivers must provide gem_init_object() and
|
||||
gem_free_object() callbacks to support the core memory
|
||||
allocation routines. They should also provide several driver
|
||||
specific ioctls to support command execution, pinning, buffer
|
||||
allocation routines. They should also provide several driver-specific
|
||||
ioctls to support command execution, pinning, buffer
|
||||
read & write, mapping, and domain ownership transfers.
|
||||
</para>
|
||||
<para>
|
||||
On a fundamental level, GEM involves several operations: memory
|
||||
allocation and freeing, command execution, and aperture management
|
||||
at command execution time. Buffer object allocation is relatively
|
||||
On a fundamental level, GEM involves several operations:
|
||||
<itemizedlist>
|
||||
<listitem>Memory allocation and freeing</listitem>
|
||||
<listitem>Command execution</listitem>
|
||||
<listitem>Aperture management at command execution time</listitem>
|
||||
</itemizedlist>
|
||||
Buffer object allocation is relatively
|
||||
straightforward and largely provided by Linux's shmem layer, which
|
||||
provides memory to back each object. When mapped into the GTT
|
||||
or used in a command buffer, the backing pages for an object are
|
||||
flushed to memory and marked write combined so as to be coherent
|
||||
with the GPU. Likewise, when the GPU finishes rendering to an object,
|
||||
if the CPU accesses it, it must be made coherent with the CPU's view
|
||||
with the GPU. Likewise, if the CPU accesses an object after the GPU
|
||||
has finished rendering to the object, then the object must be made
|
||||
coherent with the CPU's view
|
||||
of memory, usually involving GPU cache flushing of various kinds.
|
||||
This core CPU<->GPU coherency management is provided by the GEM
|
||||
set domain function, which evaluates an object's current domain and
|
||||
This core CPU<->GPU coherency management is provided by a
|
||||
device-specific ioctl, which evaluates an object's current domain and
|
||||
performs any necessary flushing or synchronization to put the object
|
||||
into the desired coherency domain (note that the object may be busy,
|
||||
i.e. an active render target; in that case the set domain function
|
||||
will block the client and wait for rendering to complete before
|
||||
i.e. an active render target; in that case, setting the domain
|
||||
blocks the client and waits for rendering to complete before
|
||||
performing any necessary flushing operations).
|
||||
</para>
|
||||
<para>
|
||||
Perhaps the most important GEM function is providing a command
|
||||
execution interface to clients. Client programs construct command
|
||||
buffers containing references to previously allocated memory objects
|
||||
and submit them to GEM. At that point, GEM will take care to bind
|
||||
buffers containing references to previously allocated memory objects,
|
||||
and then submit them to GEM. At that point, GEM takes care to bind
|
||||
all the objects into the GTT, execute the buffer, and provide
|
||||
necessary synchronization between clients accessing the same buffers.
|
||||
This often involves evicting some objects from the GTT and re-binding
|
||||
others (a fairly expensive operation), and providing relocation
|
||||
support which hides fixed GTT offsets from clients. Clients must
|
||||
take care not to submit command buffers that reference more objects
|
||||
than can fit in the GTT or GEM will reject them and no rendering
|
||||
than can fit in the GTT; otherwise, GEM will reject them and no rendering
|
||||
will occur. Similarly, if several objects in the buffer require
|
||||
fence registers to be allocated for correct rendering (e.g. 2D blits
|
||||
on pre-965 chips), care must be taken not to require more fence
|
||||
@ -729,7 +759,7 @@ void intel_crt_init(struct drm_device *dev)
|
||||
<title>Output management</title>
|
||||
<para>
|
||||
At the core of the DRM output management code is a set of
|
||||
structures representing CRTCs, encoders and connectors.
|
||||
structures representing CRTCs, encoders, and connectors.
|
||||
</para>
|
||||
<para>
|
||||
A CRTC is an abstraction representing a part of the chip that
|
||||
@ -765,21 +795,19 @@ void intel_crt_init(struct drm_device *dev)
|
||||
<sect1>
|
||||
<title>Framebuffer management</title>
|
||||
<para>
|
||||
In order to set a mode on a given CRTC, encoder and connector
|
||||
configuration, clients need to provide a framebuffer object which
|
||||
will provide a source of pixels for the CRTC to deliver to the encoder(s)
|
||||
and ultimately the connector(s) in the configuration. A framebuffer
|
||||
is fundamentally a driver specific memory object, made into an opaque
|
||||
handle by the DRM addfb function. Once an fb has been created this
|
||||
way it can be passed to the KMS mode setting routines for use in
|
||||
a configuration.
|
||||
Clients need to provide a framebuffer object which provides a source
|
||||
of pixels for a CRTC to deliver to the encoder(s) and ultimately the
|
||||
connector(s). A framebuffer is fundamentally a driver-specific memory
|
||||
object, made into an opaque handle by the DRM's addfb() function.
|
||||
Once a framebuffer has been created this way, it may be passed to the
|
||||
KMS mode setting routines for use in a completed configuration.
|
||||
</para>
|
||||
</sect1>
|
||||
|
||||
<sect1>
|
||||
<title>Command submission & fencing</title>
|
||||
<para>
|
||||
This should cover a few device specific command submission
|
||||
This should cover a few device-specific command submission
|
||||
implementations.
|
||||
</para>
|
||||
</sect1>
|
||||
@ -789,7 +817,7 @@ void intel_crt_init(struct drm_device *dev)
|
||||
<para>
|
||||
The DRM core provides some suspend/resume code, but drivers
|
||||
wanting full suspend/resume support should provide save() and
|
||||
restore() functions. These will be called at suspend,
|
||||
restore() functions. These are called at suspend,
|
||||
hibernate, or resume time, and should perform any state save or
|
||||
restore required by your device across suspend or hibernate
|
||||
states.
|
||||
@ -812,8 +840,8 @@ void intel_crt_init(struct drm_device *dev)
|
||||
<para>
|
||||
The DRM core exports several interfaces to applications,
|
||||
generally intended to be used through corresponding libdrm
|
||||
wrapper functions. In addition, drivers export device specific
|
||||
interfaces for use by userspace drivers & device aware
|
||||
wrapper functions. In addition, drivers export device-specific
|
||||
interfaces for use by userspace drivers & device-aware
|
||||
applications through ioctls and sysfs files.
|
||||
</para>
|
||||
<para>
|
||||
@ -822,8 +850,8 @@ void intel_crt_init(struct drm_device *dev)
|
||||
management, memory management, and output management.
|
||||
</para>
|
||||
<para>
|
||||
Cover generic ioctls and sysfs layout here. Only need high
|
||||
level info, since man pages will cover the rest.
|
||||
Cover generic ioctls and sysfs layout here. We only need high-level
|
||||
info, since man pages should cover the rest.
|
||||
</para>
|
||||
</chapter>
|
||||
|
||||
|
@ -572,7 +572,7 @@ static void board_select_chip (struct mtd_info *mtd, int chip)
|
||||
</para>
|
||||
<para>
|
||||
The simplest way to activate the FLASH based bad block table support
|
||||
is to set the option NAND_USE_FLASH_BBT in the option field of
|
||||
is to set the option NAND_BBT_USE_FLASH in the bbt_option field of
|
||||
the nand chip structure before calling nand_scan(). For AG-AND
|
||||
chips is this done by default.
|
||||
This activates the default FLASH based bad block table functionality
|
||||
@ -773,20 +773,6 @@ struct nand_oobinfo {
|
||||
done according to the default builtin scheme.
|
||||
</para>
|
||||
</sect2>
|
||||
<sect2 id="User_space_placement_selection">
|
||||
<title>User space placement selection</title>
|
||||
<para>
|
||||
All non ecc functions like mtd->read and mtd->write use an internal
|
||||
structure, which can be set by an ioctl. This structure is preset
|
||||
to the autoplacement default.
|
||||
<programlisting>
|
||||
ioctl (fd, MEMSETOOBSEL, oobsel);
|
||||
</programlisting>
|
||||
oobsel is a pointer to a user supplied structure of type
|
||||
nand_oobconfig. The contents of this structure must match the
|
||||
criteria of the filesystem, which will be used. See an example in utils/nandwrite.c.
|
||||
</para>
|
||||
</sect2>
|
||||
</sect1>
|
||||
<sect1 id="Spare_area_autoplacement_default">
|
||||
<title>Spare area autoplacement default schemes</title>
|
||||
@ -1158,9 +1144,6 @@ in this page</entry>
|
||||
These constants are defined in nand.h. They are ored together to describe
|
||||
the functionality.
|
||||
<programlisting>
|
||||
/* Use a flash based bad block table. This option is parsed by the
|
||||
* default bad block table function (nand_default_bbt). */
|
||||
#define NAND_USE_FLASH_BBT 0x00010000
|
||||
/* The hw ecc generator provides a syndrome instead a ecc value on read
|
||||
* This can only work if we have the ecc bytes directly behind the
|
||||
* data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
|
||||
|
@ -1,6 +1,6 @@
|
||||
To choose IO schedulers at boot time, use the argument 'elevator=deadline'.
|
||||
'noop', 'as' and 'cfq' (the default) are also available. IO schedulers are
|
||||
assigned globally at boot time only presently.
|
||||
'noop' and 'cfq' (the default) are also available. IO schedulers are assigned
|
||||
globally at boot time only presently.
|
||||
|
||||
Each io queue has a set of io scheduler tunables associated with it. These
|
||||
tunables control how the io scheduler works. You can find these entries
|
||||
|
@ -78,6 +78,16 @@ The device naming scheme is:
|
||||
/dev/cciss/c1d1p2 Controller 1, disk 1, partition 2
|
||||
/dev/cciss/c1d1p3 Controller 1, disk 1, partition 3
|
||||
|
||||
CCISS simple mode support
|
||||
-------------------------
|
||||
|
||||
The "cciss_simple_mode=1" boot parameter may be used to prevent the driver
|
||||
from putting the controller into "performant" mode. The difference is that
|
||||
with simple mode, each command completion requires an interrupt, while with
|
||||
"performant mode" (the default, and ordinarily better performing) it is
|
||||
possible to have multiple command completions indicated by a single
|
||||
interrupt.
|
||||
|
||||
SCSI tape drive and medium changer support
|
||||
------------------------------------------
|
||||
|
||||
|
@ -454,8 +454,8 @@ mounted hierarchy, to remove a task from its current cgroup you must
|
||||
move it into a new cgroup (possibly the root cgroup) by writing to the
|
||||
new cgroup's tasks file.
|
||||
|
||||
Note: If the ns cgroup is active, moving a process to another cgroup can
|
||||
fail.
|
||||
Note: Due to some restrictions enforced by some cgroup subsystems, moving
|
||||
a process to another cgroup can fail.
|
||||
|
||||
2.3 Mounting hierarchies by name
|
||||
--------------------------------
|
||||
|
@ -33,9 +33,9 @@ demonstrate this problem using nested bash shells:
|
||||
|
||||
From a second, unrelated bash shell:
|
||||
$ kill -SIGSTOP 16690
|
||||
$ kill -SIGCONT 16990
|
||||
$ kill -SIGCONT 16690
|
||||
|
||||
<at this point 16990 exits and causes 16644 to exit too>
|
||||
<at this point 16690 exits and causes 16644 to exit too>
|
||||
|
||||
This happens because bash can observe both signals and choose how it
|
||||
responds to them.
|
||||
|
@ -418,7 +418,6 @@ total_unevictable - sum of all children's "unevictable"
|
||||
|
||||
# The following additional stats are dependent on CONFIG_DEBUG_VM.
|
||||
|
||||
inactive_ratio - VM internal parameter. (see mm/page_alloc.c)
|
||||
recent_rotated_anon - VM internal parameter. (see mm/vmscan.c)
|
||||
recent_rotated_file - VM internal parameter. (see mm/vmscan.c)
|
||||
recent_scanned_anon - VM internal parameter. (see mm/vmscan.c)
|
||||
|
@ -48,7 +48,7 @@ kernel and userspace, 'connector' is used as the interface for
|
||||
communication.
|
||||
|
||||
There are currently two userspace log implementations that leverage this
|
||||
framework - "clustered_disk" and "clustered_core". These implementations
|
||||
framework - "clustered-disk" and "clustered-core". These implementations
|
||||
provide a cluster-coherent log for shared-storage. Device-mapper mirroring
|
||||
can be used in a shared-storage environment when the cluster log implementations
|
||||
are employed.
|
||||
|
84
Documentation/device-mapper/persistent-data.txt
Normal file
84
Documentation/device-mapper/persistent-data.txt
Normal file
@ -0,0 +1,84 @@
|
||||
Introduction
|
||||
============
|
||||
|
||||
The more-sophisticated device-mapper targets require complex metadata
|
||||
that is managed in kernel. In late 2010 we were seeing that various
|
||||
different targets were rolling their own data strutures, for example:
|
||||
|
||||
- Mikulas Patocka's multisnap implementation
|
||||
- Heinz Mauelshagen's thin provisioning target
|
||||
- Another btree-based caching target posted to dm-devel
|
||||
- Another multi-snapshot target based on a design of Daniel Phillips
|
||||
|
||||
Maintaining these data structures takes a lot of work, so if possible
|
||||
we'd like to reduce the number.
|
||||
|
||||
The persistent-data library is an attempt to provide a re-usable
|
||||
framework for people who want to store metadata in device-mapper
|
||||
targets. It's currently used by the thin-provisioning target and an
|
||||
upcoming hierarchical storage target.
|
||||
|
||||
Overview
|
||||
========
|
||||
|
||||
The main documentation is in the header files which can all be found
|
||||
under drivers/md/persistent-data.
|
||||
|
||||
The block manager
|
||||
-----------------
|
||||
|
||||
dm-block-manager.[hc]
|
||||
|
||||
This provides access to the data on disk in fixed sized-blocks. There
|
||||
is a read/write locking interface to prevent concurrent accesses, and
|
||||
keep data that is being used in the cache.
|
||||
|
||||
Clients of persistent-data are unlikely to use this directly.
|
||||
|
||||
The transaction manager
|
||||
-----------------------
|
||||
|
||||
dm-transaction-manager.[hc]
|
||||
|
||||
This restricts access to blocks and enforces copy-on-write semantics.
|
||||
The only way you can get hold of a writable block through the
|
||||
transaction manager is by shadowing an existing block (ie. doing
|
||||
copy-on-write) or allocating a fresh one. Shadowing is elided within
|
||||
the same transaction so performance is reasonable. The commit method
|
||||
ensures that all data is flushed before it writes the superblock.
|
||||
On power failure your metadata will be as it was when last committed.
|
||||
|
||||
The Space Maps
|
||||
--------------
|
||||
|
||||
dm-space-map.h
|
||||
dm-space-map-metadata.[hc]
|
||||
dm-space-map-disk.[hc]
|
||||
|
||||
On-disk data structures that keep track of reference counts of blocks.
|
||||
Also acts as the allocator of new blocks. Currently two
|
||||
implementations: a simpler one for managing blocks on a different
|
||||
device (eg. thinly-provisioned data blocks); and one for managing
|
||||
the metadata space. The latter is complicated by the need to store
|
||||
its own data within the space it's managing.
|
||||
|
||||
The data structures
|
||||
-------------------
|
||||
|
||||
dm-btree.[hc]
|
||||
dm-btree-remove.c
|
||||
dm-btree-spine.c
|
||||
dm-btree-internal.h
|
||||
|
||||
Currently there is only one data structure, a hierarchical btree.
|
||||
There are plans to add more. For example, something with an
|
||||
array-like interface would see a lot of use.
|
||||
|
||||
The btree is 'hierarchical' in that you can define it to be composed
|
||||
of nested btrees, and take multiple keys. For example, the
|
||||
thin-provisioning target uses a btree with two levels of nesting.
|
||||
The first maps a device id to a mapping tree, and that in turn maps a
|
||||
virtual block to a physical block.
|
||||
|
||||
Values stored in the btrees can have arbitrary size. Keys are always
|
||||
64bits, although nesting allows you to use multiple keys.
|
285
Documentation/device-mapper/thin-provisioning.txt
Normal file
285
Documentation/device-mapper/thin-provisioning.txt
Normal file
@ -0,0 +1,285 @@
|
||||
Introduction
|
||||
============
|
||||
|
||||
This document descibes a collection of device-mapper targets that
|
||||
between them implement thin-provisioning and snapshots.
|
||||
|
||||
The main highlight of this implementation, compared to the previous
|
||||
implementation of snapshots, is that it allows many virtual devices to
|
||||
be stored on the same data volume. This simplifies administration and
|
||||
allows the sharing of data between volumes, thus reducing disk usage.
|
||||
|
||||
Another significant feature is support for an arbitrary depth of
|
||||
recursive snapshots (snapshots of snapshots of snapshots ...). The
|
||||
previous implementation of snapshots did this by chaining together
|
||||
lookup tables, and so performance was O(depth). This new
|
||||
implementation uses a single data structure to avoid this degradation
|
||||
with depth. Fragmentation may still be an issue, however, in some
|
||||
scenarios.
|
||||
|
||||
Metadata is stored on a separate device from data, giving the
|
||||
administrator some freedom, for example to:
|
||||
|
||||
- Improve metadata resilience by storing metadata on a mirrored volume
|
||||
but data on a non-mirrored one.
|
||||
|
||||
- Improve performance by storing the metadata on SSD.
|
||||
|
||||
Status
|
||||
======
|
||||
|
||||
These targets are very much still in the EXPERIMENTAL state. Please
|
||||
do not yet rely on them in production. But do experiment and offer us
|
||||
feedback. Different use cases will have different performance
|
||||
characteristics, for example due to fragmentation of the data volume.
|
||||
|
||||
If you find this software is not performing as expected please mail
|
||||
dm-devel@redhat.com with details and we'll try our best to improve
|
||||
things for you.
|
||||
|
||||
Userspace tools for checking and repairing the metadata are under
|
||||
development.
|
||||
|
||||
Cookbook
|
||||
========
|
||||
|
||||
This section describes some quick recipes for using thin provisioning.
|
||||
They use the dmsetup program to control the device-mapper driver
|
||||
directly. End users will be advised to use a higher-level volume
|
||||
manager such as LVM2 once support has been added.
|
||||
|
||||
Pool device
|
||||
-----------
|
||||
|
||||
The pool device ties together the metadata volume and the data volume.
|
||||
It maps I/O linearly to the data volume and updates the metadata via
|
||||
two mechanisms:
|
||||
|
||||
- Function calls from the thin targets
|
||||
|
||||
- Device-mapper 'messages' from userspace which control the creation of new
|
||||
virtual devices amongst other things.
|
||||
|
||||
Setting up a fresh pool device
|
||||
------------------------------
|
||||
|
||||
Setting up a pool device requires a valid metadata device, and a
|
||||
data device. If you do not have an existing metadata device you can
|
||||
make one by zeroing the first 4k to indicate empty metadata.
|
||||
|
||||
dd if=/dev/zero of=$metadata_dev bs=4096 count=1
|
||||
|
||||
The amount of metadata you need will vary according to how many blocks
|
||||
are shared between thin devices (i.e. through snapshots). If you have
|
||||
less sharing than average you'll need a larger-than-average metadata device.
|
||||
|
||||
As a guide, we suggest you calculate the number of bytes to use in the
|
||||
metadata device as 48 * $data_dev_size / $data_block_size but round it up
|
||||
to 2MB if the answer is smaller. The largest size supported is 16GB.
|
||||
|
||||
If you're creating large numbers of snapshots which are recording large
|
||||
amounts of change, you may need find you need to increase this.
|
||||
|
||||
Reloading a pool table
|
||||
----------------------
|
||||
|
||||
You may reload a pool's table, indeed this is how the pool is resized
|
||||
if it runs out of space. (N.B. While specifying a different metadata
|
||||
device when reloading is not forbidden at the moment, things will go
|
||||
wrong if it does not route I/O to exactly the same on-disk location as
|
||||
previously.)
|
||||
|
||||
Using an existing pool device
|
||||
-----------------------------
|
||||
|
||||
dmsetup create pool \
|
||||
--table "0 20971520 thin-pool $metadata_dev $data_dev \
|
||||
$data_block_size $low_water_mark"
|
||||
|
||||
$data_block_size gives the smallest unit of disk space that can be
|
||||
allocated at a time expressed in units of 512-byte sectors. People
|
||||
primarily interested in thin provisioning may want to use a value such
|
||||
as 1024 (512KB). People doing lots of snapshotting may want a smaller value
|
||||
such as 128 (64KB). If you are not zeroing newly-allocated data,
|
||||
a larger $data_block_size in the region of 256000 (128MB) is suggested.
|
||||
$data_block_size must be the same for the lifetime of the
|
||||
metadata device.
|
||||
|
||||
$low_water_mark is expressed in blocks of size $data_block_size. If
|
||||
free space on the data device drops below this level then a dm event
|
||||
will be triggered which a userspace daemon should catch allowing it to
|
||||
extend the pool device. Only one such event will be sent.
|
||||
Resuming a device with a new table itself triggers an event so the
|
||||
userspace daemon can use this to detect a situation where a new table
|
||||
already exceeds the threshold.
|
||||
|
||||
Thin provisioning
|
||||
-----------------
|
||||
|
||||
i) Creating a new thinly-provisioned volume.
|
||||
|
||||
To create a new thinly- provisioned volume you must send a message to an
|
||||
active pool device, /dev/mapper/pool in this example.
|
||||
|
||||
dmsetup message /dev/mapper/pool 0 "create_thin 0"
|
||||
|
||||
Here '0' is an identifier for the volume, a 24-bit number. It's up
|
||||
to the caller to allocate and manage these identifiers. If the
|
||||
identifier is already in use, the message will fail with -EEXIST.
|
||||
|
||||
ii) Using a thinly-provisioned volume.
|
||||
|
||||
Thinly-provisioned volumes are activated using the 'thin' target:
|
||||
|
||||
dmsetup create thin --table "0 2097152 thin /dev/mapper/pool 0"
|
||||
|
||||
The last parameter is the identifier for the thinp device.
|
||||
|
||||
Internal snapshots
|
||||
------------------
|
||||
|
||||
i) Creating an internal snapshot.
|
||||
|
||||
Snapshots are created with another message to the pool.
|
||||
|
||||
N.B. If the origin device that you wish to snapshot is active, you
|
||||
must suspend it before creating the snapshot to avoid corruption.
|
||||
This is NOT enforced at the moment, so please be careful!
|
||||
|
||||
dmsetup suspend /dev/mapper/thin
|
||||
dmsetup message /dev/mapper/pool 0 "create_snap 1 0"
|
||||
dmsetup resume /dev/mapper/thin
|
||||
|
||||
Here '1' is the identifier for the volume, a 24-bit number. '0' is the
|
||||
identifier for the origin device.
|
||||
|
||||
ii) Using an internal snapshot.
|
||||
|
||||
Once created, the user doesn't have to worry about any connection
|
||||
between the origin and the snapshot. Indeed the snapshot is no
|
||||
different from any other thinly-provisioned device and can be
|
||||
snapshotted itself via the same method. It's perfectly legal to
|
||||
have only one of them active, and there's no ordering requirement on
|
||||
activating or removing them both. (This differs from conventional
|
||||
device-mapper snapshots.)
|
||||
|
||||
Activate it exactly the same way as any other thinly-provisioned volume:
|
||||
|
||||
dmsetup create snap --table "0 2097152 thin /dev/mapper/pool 1"
|
||||
|
||||
Deactivation
|
||||
------------
|
||||
|
||||
All devices using a pool must be deactivated before the pool itself
|
||||
can be.
|
||||
|
||||
dmsetup remove thin
|
||||
dmsetup remove snap
|
||||
dmsetup remove pool
|
||||
|
||||
Reference
|
||||
=========
|
||||
|
||||
'thin-pool' target
|
||||
------------------
|
||||
|
||||
i) Constructor
|
||||
|
||||
thin-pool <metadata dev> <data dev> <data block size (sectors)> \
|
||||
<low water mark (blocks)> [<number of feature args> [<arg>]*]
|
||||
|
||||
Optional feature arguments:
|
||||
- 'skip_block_zeroing': skips the zeroing of newly-provisioned blocks.
|
||||
|
||||
Data block size must be between 64KB (128 sectors) and 1GB
|
||||
(2097152 sectors) inclusive.
|
||||
|
||||
|
||||
ii) Status
|
||||
|
||||
<transaction id> <used metadata blocks>/<total metadata blocks>
|
||||
<used data blocks>/<total data blocks> <held metadata root>
|
||||
|
||||
|
||||
transaction id:
|
||||
A 64-bit number used by userspace to help synchronise with metadata
|
||||
from volume managers.
|
||||
|
||||
used data blocks / total data blocks
|
||||
If the number of free blocks drops below the pool's low water mark a
|
||||
dm event will be sent to userspace. This event is edge-triggered and
|
||||
it will occur only once after each resume so volume manager writers
|
||||
should register for the event and then check the target's status.
|
||||
|
||||
held metadata root:
|
||||
The location, in sectors, of the metadata root that has been
|
||||
'held' for userspace read access. '-' indicates there is no
|
||||
held root. This feature is not yet implemented so '-' is
|
||||
always returned.
|
||||
|
||||
iii) Messages
|
||||
|
||||
create_thin <dev id>
|
||||
|
||||
Create a new thinly-provisioned device.
|
||||
<dev id> is an arbitrary unique 24-bit identifier chosen by
|
||||
the caller.
|
||||
|
||||
create_snap <dev id> <origin id>
|
||||
|
||||
Create a new snapshot of another thinly-provisioned device.
|
||||
<dev id> is an arbitrary unique 24-bit identifier chosen by
|
||||
the caller.
|
||||
<origin id> is the identifier of the thinly-provisioned device
|
||||
of which the new device will be a snapshot.
|
||||
|
||||
delete <dev id>
|
||||
|
||||
Deletes a thin device. Irreversible.
|
||||
|
||||
trim <dev id> <new size in sectors>
|
||||
|
||||
Delete mappings from the end of a thin device. Irreversible.
|
||||
You might want to use this if you're reducing the size of
|
||||
your thinly-provisioned device. In many cases, due to the
|
||||
sharing of blocks between devices, it is not possible to
|
||||
determine in advance how much space 'trim' will release. (In
|
||||
future a userspace tool might be able to perform this
|
||||
calculation.)
|
||||
|
||||
set_transaction_id <current id> <new id>
|
||||
|
||||
Userland volume managers, such as LVM, need a way to
|
||||
synchronise their external metadata with the internal metadata of the
|
||||
pool target. The thin-pool target offers to store an
|
||||
arbitrary 64-bit transaction id and return it on the target's
|
||||
status line. To avoid races you must provide what you think
|
||||
the current transaction id is when you change it with this
|
||||
compare-and-swap message.
|
||||
|
||||
'thin' target
|
||||
-------------
|
||||
|
||||
i) Constructor
|
||||
|
||||
thin <pool dev> <dev id>
|
||||
|
||||
pool dev:
|
||||
the thin-pool device, e.g. /dev/mapper/my_pool or 253:0
|
||||
|
||||
dev id:
|
||||
the internal device identifier of the device to be
|
||||
activated.
|
||||
|
||||
The pool doesn't store any size against the thin devices. If you
|
||||
load a thin target that is smaller than you've been using previously,
|
||||
then you'll have no access to blocks mapped beyond the end. If you
|
||||
load a target that is bigger than before, then extra blocks will be
|
||||
provisioned as and when needed.
|
||||
|
||||
If you wish to reduce the size of your thin device and potentially
|
||||
regain some space then send the 'trim' message to the pool.
|
||||
|
||||
ii) Status
|
||||
|
||||
<nr mapped sectors> <highest mapped sector>
|
8
Documentation/devicetree/bindings/arm/calxeda.txt
Normal file
8
Documentation/devicetree/bindings/arm/calxeda.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Calxeda Highbank Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
|
||||
properties.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "calxeda,highbank";
|
26
Documentation/devicetree/bindings/arm/fsl.txt
Normal file
26
Documentation/devicetree/bindings/arm/fsl.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Freescale i.MX Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
i.MX51 Babbage Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx51-babbage", "fsl,imx51";
|
||||
|
||||
i.MX53 Automotive Reference Design Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx53-ard", "fsl,imx53";
|
||||
|
||||
i.MX53 Evaluation Kit
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx53-evk", "fsl,imx53";
|
||||
|
||||
i.MX53 Quick Start Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx53-qsb", "fsl,imx53";
|
||||
|
||||
i.MX53 Smart Mobile Reference Design Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx53-smd", "fsl,imx53";
|
||||
|
||||
i.MX6 Quad SABRE Automotive Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
|
55
Documentation/devicetree/bindings/arm/gic.txt
Normal file
55
Documentation/devicetree/bindings/arm/gic.txt
Normal file
@ -0,0 +1,55 @@
|
||||
* ARM Generic Interrupt Controller
|
||||
|
||||
ARM SMP cores are often associated with a GIC, providing per processor
|
||||
interrupts (PPI), shared processor interrupts (SPI) and software
|
||||
generated interrupts (SGI).
|
||||
|
||||
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
|
||||
Secondary GICs are cascaded into the upward interrupt controller and do not
|
||||
have PPIs or SGIs.
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : should be one of:
|
||||
"arm,cortex-a9-gic"
|
||||
"arm,arm11mp-gic"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The type shall be a <u32> and the value shall be 3.
|
||||
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = low-to-high edge triggered
|
||||
2 = high-to-low edge triggered
|
||||
4 = active high level-sensitive
|
||||
8 = active low level-sensitive
|
||||
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
|
||||
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
|
||||
the interrupt is wired to that CPU. Only valid for PPI interrupts.
|
||||
|
||||
- reg : Specifies base physical address(s) and size of the GIC registers. The
|
||||
first region is the GIC distributor register base and size. The 2nd region is
|
||||
the GIC cpu interface register base and size.
|
||||
|
||||
Optional
|
||||
- interrupts : Interrupt source of the parent interrupt controller. Only
|
||||
present on secondary GICs.
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
<0xfff10100 0x100>;
|
||||
};
|
||||
|
14
Documentation/devicetree/bindings/arm/omap/dsp.txt
Normal file
14
Documentation/devicetree/bindings/arm/omap/dsp.txt
Normal file
@ -0,0 +1,14 @@
|
||||
* TI - DSP (Digital Signal Processor)
|
||||
|
||||
TI DSP included in OMAP SoC
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
|
||||
- ti,hwmods: "dsp"
|
||||
|
||||
Examples:
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
ti,hwmods = "dsp";
|
||||
};
|
19
Documentation/devicetree/bindings/arm/omap/iva.txt
Normal file
19
Documentation/devicetree/bindings/arm/omap/iva.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* TI - IVA (Imaging and Video Accelerator) subsystem
|
||||
|
||||
The IVA contain various audio, video or imaging HW accelerator
|
||||
depending of the version.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be:
|
||||
- "ti,ivahd" for OMAP4
|
||||
- "ti,iva2.2" for OMAP3
|
||||
- "ti,iva2.1" for OMAP2430
|
||||
- "ti,iva1" for OMAP2420
|
||||
- ti,hwmods: "iva"
|
||||
|
||||
Examples:
|
||||
|
||||
iva {
|
||||
compatible = "ti,ivahd", "ti,iva";
|
||||
ti,hwmods = "iva";
|
||||
};
|
19
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
Normal file
19
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* TI - L3 Network On Chip (NoC)
|
||||
|
||||
This version is an implementation of the generic NoC IP
|
||||
provided by Arteris.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
|
||||
Should be "ti,omap4-l3-noc" for OMAP4 family
|
||||
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
|
||||
|
||||
Examples:
|
||||
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
};
|
27
Documentation/devicetree/bindings/arm/omap/mpu.txt
Normal file
27
Documentation/devicetree/bindings/arm/omap/mpu.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* TI - MPU (Main Processor Unit) subsystem
|
||||
|
||||
The MPU subsystem contain one or several ARM cores
|
||||
depending of the version.
|
||||
The MPU contain CPUs, GIC, L2 cache and a local PRCM.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap3-mpu" for OMAP3
|
||||
Should be "ti,omap4-mpu" for OMAP4
|
||||
- ti,hwmods: "mpu"
|
||||
|
||||
Examples:
|
||||
|
||||
- For an OMAP4 SMP system:
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
|
||||
- For an OMAP3 monocore system:
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
43
Documentation/devicetree/bindings/arm/omap/omap.txt
Normal file
43
Documentation/devicetree/bindings/arm/omap/omap.txt
Normal file
@ -0,0 +1,43 @@
|
||||
* Texas Instruments OMAP
|
||||
|
||||
OMAP is currently using a static file per SoC family to describe the
|
||||
IPs present in the SoC.
|
||||
On top of that an omap_device is created to extend the platform_device
|
||||
capabilities and to allow binding with one or several hwmods.
|
||||
The hwmods will contain all the information to build the device:
|
||||
adresse range, irq lines, dma lines, interconnect, PRCM register,
|
||||
clock domain, input clocks.
|
||||
For the moment just point to the existing hwmod, the next step will be
|
||||
to move data from hwmod to device-tree representation.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Every devices present in OMAP SoC should be in the
|
||||
form: "ti,XXX"
|
||||
- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
|
||||
HW documentation, attached to a device. Must contain at least
|
||||
one hwmod.
|
||||
|
||||
Optional properties:
|
||||
- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
|
||||
during suspend.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
spinlock@1 {
|
||||
compatible = "ti,omap4-spinlock";
|
||||
ti,hwmods = "spinlock";
|
||||
};
|
||||
|
||||
|
||||
Boards:
|
||||
|
||||
- OMAP3 BeagleBoard : Low cost community board
|
||||
compatible = "ti,omap3-beagle", "ti,omap3"
|
||||
|
||||
- OMAP4 SDP : Software Developement Board
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430"
|
||||
|
||||
- OMAP4 PandaBoard : Low cost community board
|
||||
compatible = "ti,omap4-panda", "ti,omap4430"
|
24
Documentation/devicetree/bindings/arm/picoxcell.txt
Normal file
24
Documentation/devicetree/bindings/arm/picoxcell.txt
Normal file
@ -0,0 +1,24 @@
|
||||
Picochip picoXcell device tree bindings.
|
||||
========================================
|
||||
|
||||
Required root node properties:
|
||||
- compatible:
|
||||
- "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
|
||||
- "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
|
||||
- "picochip,pc3x3" : picoXcell PC3X3 device based board.
|
||||
- "picochip,pc3x2" : picoXcell PC3X2 device based board.
|
||||
|
||||
Timers required properties:
|
||||
- compatible = "picochip,pc3x2-timer"
|
||||
- interrupts : The single IRQ line for the timer.
|
||||
- clock-freq : The frequency in HZ of the timer.
|
||||
- reg : The register bank for the timer.
|
||||
|
||||
Note: two timers are required - one for the scheduler clock and one for the
|
||||
event tick/NOHZ.
|
||||
|
||||
VIC required properties:
|
||||
- compatible = "arm,pl192-vic".
|
||||
- interrupt-controller.
|
||||
- reg : The register bank for the device.
|
||||
- #interrupt-cells : Must be 1.
|
17
Documentation/devicetree/bindings/ata/calxeda-sata.txt
Normal file
17
Documentation/devicetree/bindings/ata/calxeda-sata.txt
Normal file
@ -0,0 +1,17 @@
|
||||
* Calxeda SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "calxeda,hb-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
Example:
|
||||
sata@ffe08000 {
|
||||
compatible = "calxeda,hb-ahci";
|
||||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
};
|
||||
|
23
Documentation/devicetree/bindings/crypto/picochip-spacc.txt
Normal file
23
Documentation/devicetree/bindings/crypto/picochip-spacc.txt
Normal file
@ -0,0 +1,23 @@
|
||||
Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
|
||||
|
||||
Picochip picoXcell devices contain crypto offload engines that may be used for
|
||||
IPSEC and femtocell layer 2 ciphering.
|
||||
|
||||
Required properties:
|
||||
- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
|
||||
"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
|
||||
- reg : Offset and length of the register set for this device
|
||||
- interrupt-parent : The interrupt controller that controls the SPAcc
|
||||
interrupt.
|
||||
- interrupts : The interrupt line from the SPAcc.
|
||||
- ref-clock : The input clock that drives the SPAcc.
|
||||
|
||||
Example SPAcc node:
|
||||
|
||||
spacc@10000 {
|
||||
compatible = "picochip,spacc-ipsec";
|
||||
reg = <0x100000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <24>;
|
||||
ref-clock = <&ipsec_clk>, "ref";
|
||||
};
|
25
Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
Normal file
25
Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
Normal file
@ -0,0 +1,25 @@
|
||||
* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,<chip>-i2c"
|
||||
- reg : Should contain I2C/HS-I2C registers location and length
|
||||
- interrupts : Should contain I2C/HS-I2C interrupt
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
|
||||
The absence of the propoerty indicates the default frequency 100 kHz.
|
||||
|
||||
Examples:
|
||||
|
||||
i2c@83fc4000 { /* I2C2 on i.MX51 */
|
||||
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x83fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
};
|
||||
|
||||
i2c@70038000 { /* HS-I2C on i.MX51 */
|
||||
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x70038000 0x4000>;
|
||||
interrupts = <64>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
39
Documentation/devicetree/bindings/i2c/samsung-i2c.txt
Normal file
39
Documentation/devicetree/bindings/i2c/samsung-i2c.txt
Normal file
@ -0,0 +1,39 @@
|
||||
* Samsung's I2C controller
|
||||
|
||||
The Samsung's I2C controller is used to interface with I2C devices.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be either of the following.
|
||||
(a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
|
||||
(b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
|
||||
- gpios: The order of the gpios should be the following: <SDA, SCL>.
|
||||
The gpio specifier depends on the gpio controller.
|
||||
|
||||
Optional properties:
|
||||
- samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not
|
||||
specified, default value is 0.
|
||||
- samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
|
||||
specified, the default value in Hz is 100000.
|
||||
|
||||
Example:
|
||||
|
||||
i2c@13870000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13870000 0x100>;
|
||||
interrupts = <345>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <100000>;
|
||||
gpios = <&gpd1 2 0 /* SDA */
|
||||
&gpd1 3 0 /* SCL */>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wm8994@1a {
|
||||
compatible = "wlf,wm8994";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
14
Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
Normal file
14
Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
Normal file
@ -0,0 +1,14 @@
|
||||
* Atmel Data Flash
|
||||
|
||||
Required properties:
|
||||
- compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash".
|
||||
|
||||
Example:
|
||||
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <1>;
|
||||
};
|
@ -0,0 +1,5 @@
|
||||
NVIDIA Tegra 2 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra20-pinmux"
|
||||
|
@ -1,3 +1,8 @@
|
||||
Freescale Reference Board Bindings
|
||||
|
||||
This document describes device tree bindings for various devices that
|
||||
exist on some Freescale reference boards.
|
||||
|
||||
* Board Control and Status (BCSR)
|
||||
|
||||
Required properties:
|
||||
@ -12,25 +17,26 @@ Example:
|
||||
reg = <f8000000 8000>;
|
||||
};
|
||||
|
||||
* Freescale on board FPGA
|
||||
* Freescale on-board FPGA
|
||||
|
||||
This is the memory-mapped registers for on board FPGA.
|
||||
|
||||
Required properities:
|
||||
- compatible : should be "fsl,fpga-pixis".
|
||||
- reg : should contain the address and the length of the FPPGA register
|
||||
set.
|
||||
- compatible: should be a board-specific string followed by a string
|
||||
indicating the type of FPGA. Example:
|
||||
"fsl,<board>-fpga", "fsl,fpga-pixis"
|
||||
- reg: should contain the address and the length of the FPGA register set.
|
||||
- interrupt-parent: should specify phandle for the interrupt controller.
|
||||
- interrupts : should specify event (wakeup) IRQ.
|
||||
- interrupts: should specify event (wakeup) IRQ.
|
||||
|
||||
Example (MPC8610HPCD):
|
||||
Example (P1022DS):
|
||||
|
||||
board-control@e8000000 {
|
||||
compatible = "fsl,fpga-pixis";
|
||||
reg = <0xe8000000 32>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 8>;
|
||||
};
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
|
||||
reg = <3 0 0x30>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 8 0 0>;
|
||||
};
|
||||
|
||||
* Freescale BCSR GPIO banks
|
||||
|
||||
|
395
Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
Normal file
395
Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
Normal file
@ -0,0 +1,395 @@
|
||||
===================================================================
|
||||
Debug Control and Status Register (DCSR) Binding
|
||||
Copyright 2011 Freescale Semiconductor Inc.
|
||||
|
||||
NOTE: The bindings described in this document are preliminary and subject
|
||||
to change. Some of the compatible strings that contain only generic names
|
||||
may turn out to be inappropriate, or need additional properties to describe
|
||||
the integration of the block with the rest of the chip.
|
||||
|
||||
=====================================================================
|
||||
Debug Control and Status Register Memory Map
|
||||
|
||||
Description
|
||||
|
||||
This node defines the base address and range for the
|
||||
defined DCSR Memory Map. Child nodes will describe the individual
|
||||
debug blocks defined within this memory space.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,dcsr" and "simple-bus".
|
||||
The DCSR space exists in the memory-mapped bus.
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
or representing physical addresses in child nodes.
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
or representing the size of physical addresses in
|
||||
child nodes.
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
range of the DCSR space.
|
||||
|
||||
EXAMPLE
|
||||
dcsr: dcsr@f00000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Event Processing Unit
|
||||
|
||||
This node represents the region of DCSR space allocated to the EPU
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,dcsr-epu"
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by the EPU.
|
||||
The value of the interrupts property consists of three
|
||||
interrupt specifiers. The format of the specifier is defined
|
||||
by the binding document describing the node's interrupt parent.
|
||||
|
||||
The EPU counters can be configured to assert the performance
|
||||
monitor interrupt signal based on either counter overflow or value
|
||||
match. Which counter asserted the interrupt is captured in an EPU
|
||||
Counter Interrupt Status Register (EPCPUISR).
|
||||
|
||||
The EPU unit can also be configured to assert either or both of
|
||||
two interrupt signals based on debug event sources within the SoC.
|
||||
The interrupt signals are epu_xt_int0 and epu_xt_int1.
|
||||
Which event source asserted the interrupt is captured in an EPU
|
||||
Interrupt Status Register (EPISR0,EPISR1).
|
||||
|
||||
Interrupt numbers are lised in order (perfmon, event0, event1).
|
||||
|
||||
- interrupt-parent
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: A single <phandle> value that points
|
||||
to the interrupt parent to which the child domain
|
||||
is being mapped. Value must be "&mpic"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
Nexus Port Controller
|
||||
|
||||
This node represents the region of DCSR space allocated to the NPC
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,dcsr-npc"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
The Nexus Port controller occupies two regions in the DCSR space
|
||||
with distinct functionality.
|
||||
|
||||
The first register range describes the Nexus Port Controller
|
||||
control and status registers.
|
||||
|
||||
The second register range describes the Nexus Port Controller
|
||||
internal trace buffer. The NPC trace buffer is a small memory buffer
|
||||
which stages the nexus trace data for transmission via the Aurora port
|
||||
or to a DDR based trace buffer. In some configurations the NPC trace
|
||||
buffer can be the only trace buffer used.
|
||||
|
||||
|
||||
EXAMPLE
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
Nexus Concentrator
|
||||
|
||||
This node represents the region of DCSR space allocated to the NXC
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,dcsr-nxc"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
=======================================================================
|
||||
CoreNet Debug Controller
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the CoreNet Debug controller.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,dcsr-corenet"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
The CoreNet Debug controller occupies two regions in the DCSR space
|
||||
with distinct functionality.
|
||||
|
||||
The first register range describes the CoreNet Debug Controller
|
||||
functionalty to perform transaction and transaction attribute matches.
|
||||
|
||||
The second register range describes the CoreNet Debug Controller
|
||||
functionalty to trigger event notifications and debug traces.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
Data Path Debug controller
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the DPAA Debug Controller. This controller controls debug configuration
|
||||
for the QMAN and FMAN blocks.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include both an identifier specific to the SoC
|
||||
or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
|
||||
generic compatible string "fsl,dcsr-dpaa".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
OCeaN Debug controller
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the OCN Debug Controller.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include both an identifier specific to the SoC
|
||||
or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
|
||||
generic compatible string "fsl,dcsr-ocn".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
DDR Controller Debug controller
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the OCN Debug Controller.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,dcsr-ddr"
|
||||
|
||||
- dev-handle
|
||||
Usage: required
|
||||
Definition: A phandle to associate this debug node with its
|
||||
component controller.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
Nexus Aurora Link Controller
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the NAL Controller.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include both an identifier specific to the SoC
|
||||
or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
|
||||
generic compatible string "fsl,dcsr-nal".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
|
||||
|
||||
=======================================================================
|
||||
Run Control and Power Management
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the RCPM Debug Controller. This functionlity is limited to the
|
||||
control the debug operations of the SoC and cores.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include both an identifier specific to the SoC
|
||||
or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
|
||||
generic compatible string "fsl,dcsr-rcpm".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
||||
Core Service Bridge Proxy
|
||||
|
||||
This node represents the region of DCSR space allocated to
|
||||
the Core Service Bridge Proxies.
|
||||
There is one Core Service Bridge Proxy device for each CPU in the system.
|
||||
This functionlity provides access to the debug operations of the CPU.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include both an identifier specific to the cpu
|
||||
of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
|
||||
generic compatible string "fsl,dcsr-cpu-sb-proxy".
|
||||
|
||||
- cpu-handle
|
||||
Usage: required
|
||||
Definition: A phandle to associate this debug node with its cpu.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
offset and length of the DCSR space registers of the device
|
||||
configuration block.
|
||||
|
||||
EXAMPLE
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy",
|
||||
"fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy",
|
||||
"fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
|
||||
=======================================================================
|
@ -25,6 +25,16 @@ Required properties:
|
||||
are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
|
||||
to MPIC.
|
||||
|
||||
Optional properties:
|
||||
- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
|
||||
is used for MSI messaging. The address of MSIIR in PCI address space is
|
||||
the MSI message address.
|
||||
|
||||
This property may be used in virtualized environments where the hypervisor
|
||||
has created an alternate mapping for the MSIR block. See below for an
|
||||
explanation.
|
||||
|
||||
|
||||
Example:
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
|
||||
@ -41,3 +51,35 @@ Example:
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
The Freescale hypervisor and msi-address-64
|
||||
-------------------------------------------
|
||||
Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
|
||||
Freescale MSI driver calculates the address of MSIIR (in the MSI register
|
||||
block) and sets that address as the MSI message address.
|
||||
|
||||
In a virtualized environment, the hypervisor may need to create an IOMMU
|
||||
mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
|
||||
because of hardware limitations of the Peripheral Access Management Unit
|
||||
(PAMU), which is currently the only IOMMU that the hypervisor supports.
|
||||
The ATMU is programmed with the guest physical address, and the PAMU
|
||||
intercepts transactions and reroutes them to the true physical address.
|
||||
|
||||
In the PAMU, each PCI controller is given only one primary window. The
|
||||
PAMU restricts DMA operations so that they can only occur within a window.
|
||||
Because PCI devices must be able to DMA to memory, the primary window must
|
||||
be used to cover all of the guest's memory space.
|
||||
|
||||
PAMU primary windows can be divided into 256 subwindows, and each
|
||||
subwindow can have its own address mapping ("guest physical" to "true
|
||||
physical"). However, each subwindow has to have the same alignment, which
|
||||
means they cannot be located at just any address. Because of these
|
||||
restrictions, it is usually impossible to create a 4KB subwindow that
|
||||
covers MSIIR where it's normally located.
|
||||
|
||||
Therefore, the hypervisor has to create a subwindow inside the same
|
||||
primary window used for memory, but mapped to the MSIR block (where MSIIR
|
||||
lives). The first subwindow after the end of guest memory is used for
|
||||
this. The address specified in the msi-address-64 property is the PCI
|
||||
address of MSIIR. The hypervisor configures the PAMU to map that address to
|
||||
the true physical address of MSIIR.
|
||||
|
27
Documentation/devicetree/bindings/tty/serial/msm_serial.txt
Normal file
27
Documentation/devicetree/bindings/tty/serial/msm_serial.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* Qualcomm MSM UART
|
||||
|
||||
Required properties:
|
||||
- compatible :
|
||||
- "qcom,msm-uart", and one of "qcom,msm-hsuart" or
|
||||
"qcom,msm-lsuart".
|
||||
- reg : offset and length of the register set for the device
|
||||
for the hsuart operating in compatible mode, there should be a
|
||||
second pair describing the gsbi registers.
|
||||
- interrupts : should contain the uart interrupt.
|
||||
|
||||
There are two different UART blocks used in MSM devices,
|
||||
"qcom,msm-hsuart" and "qcom,msm-lsuart". The msm-serial driver is
|
||||
able to handle both of these, and matches against the "qcom,msm-uart"
|
||||
as the compatibility.
|
||||
|
||||
The registers for the "qcom,msm-hsuart" device need to specify both
|
||||
register blocks, even for the common driver.
|
||||
|
||||
Example:
|
||||
|
||||
uart@19c400000 {
|
||||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <195>;
|
||||
};
|
17
Documentation/devicetree/bindings/virtio/mmio.txt
Normal file
17
Documentation/devicetree/bindings/virtio/mmio.txt
Normal file
@ -0,0 +1,17 @@
|
||||
* virtio memory mapped device
|
||||
|
||||
See http://ozlabs.org/~rusty/virtio-spec/ for more details.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "virtio,mmio" compatibility string
|
||||
- reg: control registers base address and size including configuration space
|
||||
- interrupts: interrupt generated by the device
|
||||
|
||||
Example:
|
||||
|
||||
virtio_block@3000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <41>;
|
||||
}
|
@ -133,41 +133,6 @@ Who: Pavel Machek <pavel@ucw.cz>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: sys_sysctl
|
||||
When: September 2010
|
||||
Option: CONFIG_SYSCTL_SYSCALL
|
||||
Why: The same information is available in a more convenient from
|
||||
/proc/sys, and none of the sysctl variables appear to be
|
||||
important performance wise.
|
||||
|
||||
Binary sysctls are a long standing source of subtle kernel
|
||||
bugs and security issues.
|
||||
|
||||
When I looked several months ago all I could find after
|
||||
searching several distributions were 5 user space programs and
|
||||
glibc (which falls back to /proc/sys) using this syscall.
|
||||
|
||||
The man page for sysctl(2) documents it as unusable for user
|
||||
space programs.
|
||||
|
||||
sysctl(2) is not generally ABI compatible to a 32bit user
|
||||
space application on a 64bit and a 32bit kernel.
|
||||
|
||||
For the last several months the policy has been no new binary
|
||||
sysctls and no one has put forward an argument to use them.
|
||||
|
||||
Binary sysctls issues seem to keep happening appearing so
|
||||
properly deprecating them (with a warning to user space) and a
|
||||
2 year grace warning period will mean eventually we can kill
|
||||
them and end the pain.
|
||||
|
||||
In the mean time individual binary sysctls can be dealt with
|
||||
in a piecewise fashion.
|
||||
|
||||
Who: Eric Biederman <ebiederm@xmission.com>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: /proc/<pid>/oom_adj
|
||||
When: August 2012
|
||||
Why: /proc/<pid>/oom_adj allows userspace to influence the oom killer's
|
||||
|
@ -29,6 +29,7 @@ d_hash no no no maybe
|
||||
d_compare: yes no no maybe
|
||||
d_delete: no yes no no
|
||||
d_release: no no yes no
|
||||
d_prune: no yes no no
|
||||
d_iput: no no yes no
|
||||
d_dname: no no no no
|
||||
d_automount: no no yes no
|
||||
|
@ -73,14 +73,6 @@ nobarrier (*) This also requires an IO stack which can support
|
||||
also be used to enable or disable barriers, for
|
||||
consistency with other ext3 mount options.
|
||||
|
||||
orlov (*) This enables the new Orlov block allocator. It is
|
||||
enabled by default.
|
||||
|
||||
oldalloc This disables the Orlov block allocator and enables
|
||||
the old block allocator. Orlov should have better
|
||||
performance - we'd like to get some feedback if it's
|
||||
the contrary for you.
|
||||
|
||||
user_xattr Enables Extended User Attributes. Additionally, you
|
||||
need to have extended attribute support enabled in the
|
||||
kernel configuration (CONFIG_EXT3_FS_XATTR). See the
|
||||
|
@ -160,7 +160,9 @@ noload if the filesystem was not unmounted cleanly,
|
||||
lead to any number of problems.
|
||||
|
||||
data=journal All data are committed into the journal prior to being
|
||||
written into the main file system.
|
||||
written into the main file system. Enabling
|
||||
this mode will disable delayed allocation and
|
||||
O_DIRECT support.
|
||||
|
||||
data=ordered (*) All data are forced directly out to the main file
|
||||
system prior to its metadata being committed to the
|
||||
@ -201,30 +203,19 @@ inode_readahead_blks=n This tuning parameter controls the maximum
|
||||
table readahead algorithm will pre-read into
|
||||
the buffer cache. The default value is 32 blocks.
|
||||
|
||||
orlov (*) This enables the new Orlov block allocator. It is
|
||||
enabled by default.
|
||||
|
||||
oldalloc This disables the Orlov block allocator and enables
|
||||
the old block allocator. Orlov should have better
|
||||
performance - we'd like to get some feedback if it's
|
||||
the contrary for you.
|
||||
|
||||
user_xattr Enables Extended User Attributes. Additionally, you
|
||||
need to have extended attribute support enabled in the
|
||||
kernel configuration (CONFIG_EXT4_FS_XATTR). See the
|
||||
attr(5) manual page and http://acl.bestbits.at/ to
|
||||
learn more about extended attributes.
|
||||
|
||||
nouser_xattr Disables Extended User Attributes.
|
||||
|
||||
acl Enables POSIX Access Control Lists support.
|
||||
Additionally, you need to have ACL support enabled in
|
||||
the kernel configuration (CONFIG_EXT4_FS_POSIX_ACL).
|
||||
See the acl(5) manual page and http://acl.bestbits.at/
|
||||
for more information.
|
||||
nouser_xattr Disables Extended User Attributes. If you have extended
|
||||
attribute support enabled in the kernel configuration
|
||||
(CONFIG_EXT4_FS_XATTR), extended attribute support
|
||||
is enabled by default on mount. See the attr(5) manual
|
||||
page and http://acl.bestbits.at/ for more information
|
||||
about extended attributes.
|
||||
|
||||
noacl This option disables POSIX Access Control List
|
||||
support.
|
||||
support. If ACL support is enabled in the kernel
|
||||
configuration (CONFIG_EXT4_FS_POSIX_ACL), ACL is
|
||||
enabled by default on mount. See the acl(5) manual
|
||||
page and http://acl.bestbits.at/ for more information
|
||||
about acl.
|
||||
|
||||
bsddf (*) Make 'df' act like BSD.
|
||||
minixdf Make 'df' act like Minix.
|
||||
@ -419,8 +410,8 @@ written to the journal first, and then to its final location.
|
||||
In the event of a crash, the journal can be replayed, bringing both data and
|
||||
metadata into a consistent state. This mode is the slowest except when data
|
||||
needs to be read from and written to disk at the same time where it
|
||||
outperforms all others modes. Currently ext4 does not have delayed
|
||||
allocation support if this data journalling mode is selected.
|
||||
outperforms all others modes. Enabling this mode will disable delayed
|
||||
allocation and O_DIRECT support.
|
||||
|
||||
/proc entries
|
||||
=============
|
||||
|
@ -1,3 +1,4 @@
|
||||
Note: This filesystem doesn't have a maintainer.
|
||||
|
||||
Macintosh HFS Filesystem for Linux
|
||||
==================================
|
||||
@ -76,8 +77,6 @@ hformat that can be used to create HFS filesystem. See
|
||||
Credits
|
||||
=======
|
||||
|
||||
The HFS drivers was written by Paul H. Hargrovea (hargrove@sccm.Stanford.EDU)
|
||||
and is now maintained by Roman Zippel (roman@ardistech.com) at Ardis
|
||||
Technologies.
|
||||
Roman rewrote large parts of the code and brought in btree routines derived
|
||||
from Brad Boyer's hfsplus driver (also maintained by Roman now).
|
||||
The HFS drivers was written by Paul H. Hargrovea (hargrove@sccm.Stanford.EDU).
|
||||
Roman Zippel (roman@ardistech.com) rewrote large parts of the code and brought
|
||||
in btree routines derived from Brad Boyer's hfsplus driver.
|
||||
|
@ -194,7 +194,8 @@ associated with the inotify_handle, and on which events are queued.
|
||||
Each watch is associated with an inotify_watch structure. Watches are chained
|
||||
off of each associated inotify_handle and each associated inode.
|
||||
|
||||
See fs/inotify.c and fs/inotify_user.c for the locking and lifetime rules.
|
||||
See fs/notify/inotify/inotify_fsnotify.c and fs/notify/inotify/inotify_user.c
|
||||
for the locking and lifetime rules.
|
||||
|
||||
|
||||
(vi) Rationale
|
||||
|
@ -14,6 +14,10 @@ Supported chips:
|
||||
Prefix: 'w83627dhg'
|
||||
Addresses scanned: ISA address retrieved from Super I/O registers
|
||||
Datasheet: not available
|
||||
* Winbond W83627UHG
|
||||
Prefix: 'w83627uhg'
|
||||
Addresses scanned: ISA address retrieved from Super I/O registers
|
||||
Datasheet: available from www.nuvoton.com
|
||||
* Winbond W83667HG
|
||||
Prefix: 'w83667hg'
|
||||
Addresses scanned: ISA address retrieved from Super I/O registers
|
||||
@ -42,14 +46,13 @@ Description
|
||||
-----------
|
||||
|
||||
This driver implements support for the Winbond W83627EHF, W83627EHG,
|
||||
W83627DHG, W83627DHG-P, W83667HG, W83667HG-B, W83667HG-I (NCT6775F),
|
||||
and NCT6776F super I/O chips. We will refer to them collectively as
|
||||
Winbond chips.
|
||||
W83627DHG, W83627DHG-P, W83627UHG, W83667HG, W83667HG-B, W83667HG-I
|
||||
(NCT6775F), and NCT6776F super I/O chips. We will refer to them collectively
|
||||
as Winbond chips.
|
||||
|
||||
The chips implement three temperature sensors (up to four for 667HG-B, and nine
|
||||
for NCT6775F and NCT6776F), five fan rotation speed sensors, ten analog voltage
|
||||
sensors (only nine for the 627DHG), one VID (6 pins for the 627EHF/EHG, 8 pins
|
||||
for the 627DHG and 667HG), alarms with beep warnings (control unimplemented),
|
||||
The chips implement 2 to 4 temperature sensors (9 for NCT6775F and NCT6776F),
|
||||
2 to 5 fan rotation speed sensors, 8 to 10 analog voltage sensors, one VID
|
||||
(except for 627UHG), alarms with beep warnings (control unimplemented),
|
||||
and some automatic fan regulation strategies (plus manual fan control mode).
|
||||
|
||||
The temperature sensor sources on W82677HG-B, NCT6775F, and NCT6776F are
|
||||
@ -86,17 +89,16 @@ follows:
|
||||
|
||||
temp1 -> pwm1
|
||||
temp2 -> pwm2
|
||||
temp3 -> pwm3
|
||||
temp3 -> pwm3 (not on 627UHG)
|
||||
prog -> pwm4 (not on 667HG and 667HG-B; the programmable setting is not
|
||||
supported by the driver)
|
||||
|
||||
/sys files
|
||||
----------
|
||||
|
||||
name - this is a standard hwmon device entry. For the W83627EHF and W83627EHG,
|
||||
it is set to "w83627ehf", for the W83627DHG it is set to "w83627dhg",
|
||||
for the W83667HG and W83667HG-B it is set to "w83667hg", for NCT6775F it
|
||||
is set to "nct6775", and for NCT6776F it is set to "nct6776".
|
||||
name - this is a standard hwmon device entry, it contains the name of
|
||||
the device (see the prefix in the list of supported devices at
|
||||
the top of this file)
|
||||
|
||||
pwm[1-4] - this file stores PWM duty cycle or DC value (fan speed) in range:
|
||||
0 (stop) to 255 (full)
|
||||
|
@ -39,23 +39,20 @@ independent, drivers.
|
||||
in case an unused hwspinlock isn't available. Users of this
|
||||
API will usually want to communicate the lock's id to the remote core
|
||||
before it can be used to achieve synchronization.
|
||||
Can be called from an atomic context (this function will not sleep) but
|
||||
not from within interrupt context.
|
||||
Should be called from a process context (might sleep).
|
||||
|
||||
struct hwspinlock *hwspin_lock_request_specific(unsigned int id);
|
||||
- assign a specific hwspinlock id and return its address, or NULL
|
||||
if that hwspinlock is already in use. Usually board code will
|
||||
be calling this function in order to reserve specific hwspinlock
|
||||
ids for predefined purposes.
|
||||
Can be called from an atomic context (this function will not sleep) but
|
||||
not from within interrupt context.
|
||||
Should be called from a process context (might sleep).
|
||||
|
||||
int hwspin_lock_free(struct hwspinlock *hwlock);
|
||||
- free a previously-assigned hwspinlock; returns 0 on success, or an
|
||||
appropriate error code on failure (e.g. -EINVAL if the hwspinlock
|
||||
is already free).
|
||||
Can be called from an atomic context (this function will not sleep) but
|
||||
not from within interrupt context.
|
||||
Should be called from a process context (might sleep).
|
||||
|
||||
int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout);
|
||||
- lock a previously-assigned hwspinlock with a timeout limit (specified in
|
||||
@ -230,45 +227,62 @@ int hwspinlock_example2(void)
|
||||
|
||||
4. API for implementors
|
||||
|
||||
int hwspin_lock_register(struct hwspinlock *hwlock);
|
||||
int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev,
|
||||
const struct hwspinlock_ops *ops, int base_id, int num_locks);
|
||||
- to be called from the underlying platform-specific implementation, in
|
||||
order to register a new hwspinlock instance. Can be called from an atomic
|
||||
context (this function will not sleep) but not from within interrupt
|
||||
context. Returns 0 on success, or appropriate error code on failure.
|
||||
order to register a new hwspinlock device (which is usually a bank of
|
||||
numerous locks). Should be called from a process context (this function
|
||||
might sleep).
|
||||
Returns 0 on success, or appropriate error code on failure.
|
||||
|
||||
struct hwspinlock *hwspin_lock_unregister(unsigned int id);
|
||||
int hwspin_lock_unregister(struct hwspinlock_device *bank);
|
||||
- to be called from the underlying vendor-specific implementation, in order
|
||||
to unregister an existing (and unused) hwspinlock instance.
|
||||
Can be called from an atomic context (will not sleep) but not from
|
||||
within interrupt context.
|
||||
to unregister an hwspinlock device (which is usually a bank of numerous
|
||||
locks).
|
||||
Should be called from a process context (this function might sleep).
|
||||
Returns the address of hwspinlock on success, or NULL on error (e.g.
|
||||
if the hwspinlock is sill in use).
|
||||
|
||||
5. struct hwspinlock
|
||||
5. Important structs
|
||||
|
||||
This struct represents an hwspinlock instance. It is registered by the
|
||||
underlying hwspinlock implementation using the hwspin_lock_register() API.
|
||||
struct hwspinlock_device is a device which usually contains a bank
|
||||
of hardware locks. It is registered by the underlying hwspinlock
|
||||
implementation using the hwspin_lock_register() API.
|
||||
|
||||
/**
|
||||
* struct hwspinlock - vendor-specific hwspinlock implementation
|
||||
*
|
||||
* @dev: underlying device, will be used with runtime PM api
|
||||
* @ops: vendor-specific hwspinlock handlers
|
||||
* @id: a global, unique, system-wide, index of the lock.
|
||||
* @lock: initialized and used by hwspinlock core
|
||||
* @owner: underlying implementation module, used to maintain module ref count
|
||||
* struct hwspinlock_device - a device which usually spans numerous hwspinlocks
|
||||
* @dev: underlying device, will be used to invoke runtime PM api
|
||||
* @ops: platform-specific hwspinlock handlers
|
||||
* @base_id: id index of the first lock in this device
|
||||
* @num_locks: number of locks in this device
|
||||
* @lock: dynamically allocated array of 'struct hwspinlock'
|
||||
*/
|
||||
struct hwspinlock {
|
||||
struct hwspinlock_device {
|
||||
struct device *dev;
|
||||
const struct hwspinlock_ops *ops;
|
||||
int id;
|
||||
spinlock_t lock;
|
||||
struct module *owner;
|
||||
int base_id;
|
||||
int num_locks;
|
||||
struct hwspinlock lock[0];
|
||||
};
|
||||
|
||||
The underlying implementation is responsible to assign the dev, ops, id and
|
||||
owner members. The lock member, OTOH, is initialized and used by the hwspinlock
|
||||
core.
|
||||
struct hwspinlock_device contains an array of hwspinlock structs, each
|
||||
of which represents a single hardware lock:
|
||||
|
||||
/**
|
||||
* struct hwspinlock - this struct represents a single hwspinlock instance
|
||||
* @bank: the hwspinlock_device structure which owns this lock
|
||||
* @lock: initialized and used by hwspinlock core
|
||||
* @priv: private data, owned by the underlying platform-specific hwspinlock drv
|
||||
*/
|
||||
struct hwspinlock {
|
||||
struct hwspinlock_device *bank;
|
||||
spinlock_t lock;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
When registering a bank of locks, the hwspinlock driver only needs to
|
||||
set the priv members of the locks. The rest of the members are set and
|
||||
initialized by the hwspinlock core itself.
|
||||
|
||||
6. Implementation callbacks
|
||||
|
||||
|
@ -741,10 +741,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
||||
See Documentation/block/cfq-iosched.txt and
|
||||
Documentation/block/deadline-iosched.txt for details.
|
||||
|
||||
elfcorehdr= [IA-64,PPC,SH,X86]
|
||||
elfcorehdr=[size[KMG]@]offset[KMG] [IA64,PPC,SH,X86,S390]
|
||||
Specifies physical address of start of kernel core
|
||||
image elf header. Generally kexec loader will
|
||||
pass this option to capture kernel.
|
||||
image elf header and optionally the size. Generally
|
||||
kexec loader will pass this option to capture kernel.
|
||||
See Documentation/kdump/kdump.txt for details.
|
||||
|
||||
enable_mtrr_cleanup [X86]
|
||||
@ -973,6 +973,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
||||
ignore_loglevel [KNL]
|
||||
Ignore loglevel setting - this will print /all/
|
||||
kernel messages to the console. Useful for debugging.
|
||||
We also add it as printk module parameter, so users
|
||||
could change it dynamically, usually by
|
||||
/sys/module/printk/parameters/ignore_loglevel.
|
||||
|
||||
ihash_entries= [KNL]
|
||||
Set number of hash buckets for inode cache.
|
||||
@ -1666,6 +1669,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
||||
debugging driver suspend/resume hooks). This may
|
||||
not work reliably with all consoles, but is known
|
||||
to work with serial and VGA consoles.
|
||||
To facilitate more flexible debugging, we also add
|
||||
console_suspend, a printk module parameter to control
|
||||
it. Users could use console_suspend (usually
|
||||
/sys/module/printk/parameters/console_suspend) to
|
||||
turn on/off it dynamically.
|
||||
|
||||
noaliencache [MM, NUMA, SLAB] Disables the allocation of alien
|
||||
caches in the slab allocator. Saves per-node memory,
|
||||
|
@ -411,9 +411,9 @@ event code Key Notes
|
||||
|
||||
0x1004 0x03 FN+F4 Sleep button (ACPI sleep button
|
||||
semantics, i.e. sleep-to-RAM).
|
||||
It is always generate some kind
|
||||
It always generates some kind
|
||||
of event, either the hot key
|
||||
event or a ACPI sleep button
|
||||
event or an ACPI sleep button
|
||||
event. The firmware may
|
||||
refuse to generate further FN+F4
|
||||
key presses until a S3 or S4 ACPI
|
||||
|
@ -61,8 +61,8 @@ Hardware accelerated blink of LEDs
|
||||
Some LEDs can be programmed to blink without any CPU interaction. To
|
||||
support this feature, a LED driver can optionally implement the
|
||||
blink_set() function (see <linux/leds.h>). To set an LED to blinking,
|
||||
however, it is better to use use the API function led_blink_set(),
|
||||
as it will check and implement software fallback if necessary.
|
||||
however, it is better to use the API function led_blink_set(), as it
|
||||
will check and implement software fallback if necessary.
|
||||
|
||||
To turn off blinking again, use the API function led_brightness_set()
|
||||
as that will not just set the LED brightness but also stop any software
|
||||
|
@ -15,6 +15,23 @@ amemthresh - INTEGER
|
||||
enabled and the variable is automatically set to 2, otherwise
|
||||
the strategy is disabled and the variable is set to 1.
|
||||
|
||||
conntrack - BOOLEAN
|
||||
0 - disabled (default)
|
||||
not 0 - enabled
|
||||
|
||||
If set, maintain connection tracking entries for
|
||||
connections handled by IPVS.
|
||||
|
||||
This should be enabled if connections handled by IPVS are to be
|
||||
also handled by stateful firewall rules. That is, iptables rules
|
||||
that make use of connection tracking. It is a performance
|
||||
optimisation to disable this setting otherwise.
|
||||
|
||||
Connections handled by the IPVS FTP application module
|
||||
will have connection tracking entries regardless of this setting.
|
||||
|
||||
Only available when IPVS is compiled with CONFIG_IP_VS_NFCT enabled.
|
||||
|
||||
cache_bypass - BOOLEAN
|
||||
0 - disabled (default)
|
||||
not 0 - enabled
|
||||
@ -39,7 +56,7 @@ debug_level - INTEGER
|
||||
11 - IPVS packet handling (ip_vs_in/ip_vs_out)
|
||||
12 or more - packet traversal
|
||||
|
||||
Only available when IPVS is compiled with the CONFIG_IPVS_DEBUG
|
||||
Only available when IPVS is compiled with CONFIG_IP_VS_DEBUG enabled.
|
||||
|
||||
Higher debugging levels include the messages for lower debugging
|
||||
levels, so setting debug level 2, includes level 0, 1 and 2
|
||||
@ -123,13 +140,11 @@ nat_icmp_send - BOOLEAN
|
||||
secure_tcp - INTEGER
|
||||
0 - disabled (default)
|
||||
|
||||
The secure_tcp defense is to use a more complicated state
|
||||
transition table and some possible short timeouts of each
|
||||
state. In the VS/NAT, it delays the entering the ESTABLISHED
|
||||
until the real server starts to send data and ACK packet
|
||||
(after 3-way handshake).
|
||||
The secure_tcp defense is to use a more complicated TCP state
|
||||
transition table. For VS/NAT, it also delays entering the
|
||||
TCP ESTABLISHED state until the three way handshake is completed.
|
||||
|
||||
The value definition is the same as that of drop_entry or
|
||||
The value definition is the same as that of drop_entry and
|
||||
drop_packet.
|
||||
|
||||
sync_threshold - INTEGER
|
||||
@ -141,3 +156,36 @@ sync_threshold - INTEGER
|
||||
synchronized, every time the number of its incoming packets
|
||||
modulus 50 equals the threshold. The range of the threshold is
|
||||
from 0 to 49.
|
||||
|
||||
snat_reroute - BOOLEAN
|
||||
0 - disabled
|
||||
not 0 - enabled (default)
|
||||
|
||||
If enabled, recalculate the route of SNATed packets from
|
||||
realservers so that they are routed as if they originate from the
|
||||
director. Otherwise they are routed as if they are forwarded by the
|
||||
director.
|
||||
|
||||
If policy routing is in effect then it is possible that the route
|
||||
of a packet originating from a director is routed differently to a
|
||||
packet being forwarded by the director.
|
||||
|
||||
If policy routing is not in effect then the recalculated route will
|
||||
always be the same as the original route so it is an optimisation
|
||||
to disable snat_reroute and avoid the recalculation.
|
||||
|
||||
sync_version - INTEGER
|
||||
default 1
|
||||
|
||||
The version of the synchronisation protocol used when sending
|
||||
synchronisation messages.
|
||||
|
||||
0 selects the original synchronisation protocol (version 0). This
|
||||
should be used when sending synchronisation messages to a legacy
|
||||
system that only understands the original synchronisation protocol.
|
||||
|
||||
1 selects the current synchronisation protocol (version 1). This
|
||||
should be used where possible.
|
||||
|
||||
Kernels with this sync_version entry are able to receive messages
|
||||
of both version 1 and version 2 of the synchronisation protocol.
|
||||
|
@ -263,6 +263,8 @@ characters, each representing a particular tainted value.
|
||||
12: 'I' if the kernel is working around a severe bug in the platform
|
||||
firmware (BIOS or similar).
|
||||
|
||||
13: 'O' if an externally-built ("out-of-tree") module has been loaded.
|
||||
|
||||
The primary reason for the 'Tainted: ' string is to tell kernel
|
||||
debuggers if this is a clean kernel or if anything unusual has
|
||||
occurred. Tainting is permanent: even if an offending module is
|
||||
|
@ -22,12 +22,12 @@ try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
|
||||
either wakes them up, if they are kernel threads, or sends fake signals to them,
|
||||
if they are user space processes. A task that has TIF_FREEZE set, should react
|
||||
to it by calling the function called refrigerator() (defined in
|
||||
kernel/power/process.c), which sets the task's PF_FROZEN flag, changes its state
|
||||
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
|
||||
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
|
||||
Then, we say that the task is 'frozen' and therefore the set of functions
|
||||
handling this mechanism is referred to as 'the freezer' (these functions are
|
||||
defined in kernel/power/process.c and include/linux/freezer.h). User space
|
||||
processes are generally frozen before kernel threads.
|
||||
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
|
||||
User space processes are generally frozen before kernel threads.
|
||||
|
||||
It is not recommended to call refrigerator() directly. Instead, it is
|
||||
recommended to use the try_to_freeze() function (defined in
|
||||
@ -95,7 +95,7 @@ after the memory for the image has been freed, we don't want tasks to allocate
|
||||
additional memory and we prevent them from doing that by freezing them earlier.
|
||||
[Of course, this also means that device drivers should not allocate substantial
|
||||
amounts of memory from their .suspend() callbacks before hibernation, but this
|
||||
is e separate issue.]
|
||||
is a separate issue.]
|
||||
|
||||
3. The third reason is to prevent user space processes and some kernel threads
|
||||
from interfering with the suspending and resuming of devices. A user space
|
||||
|
@ -16,7 +16,7 @@ initialisation code by creating a struct regulator_consumer_supply for
|
||||
each regulator.
|
||||
|
||||
struct regulator_consumer_supply {
|
||||
struct device *dev; /* consumer */
|
||||
const char *dev_name; /* consumer dev_name() */
|
||||
const char *supply; /* consumer supply - e.g. "vcc" */
|
||||
};
|
||||
|
||||
@ -24,13 +24,13 @@ e.g. for the machine above
|
||||
|
||||
static struct regulator_consumer_supply regulator1_consumers[] = {
|
||||
{
|
||||
.dev = &platform_consumerB_device.dev,
|
||||
.supply = "Vcc",
|
||||
.dev_name = "dev_name(consumer B)",
|
||||
.supply = "Vcc",
|
||||
},};
|
||||
|
||||
static struct regulator_consumer_supply regulator2_consumers[] = {
|
||||
{
|
||||
.dev = &platform_consumerA_device.dev,
|
||||
.dev = "dev_name(consumer A"),
|
||||
.supply = "Vcc",
|
||||
},};
|
||||
|
||||
@ -43,6 +43,7 @@ to their supply regulator :-
|
||||
|
||||
static struct regulator_init_data regulator1_data = {
|
||||
.constraints = {
|
||||
.name = "Regulator-1",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
@ -51,13 +52,19 @@ static struct regulator_init_data regulator1_data = {
|
||||
.consumer_supplies = regulator1_consumers,
|
||||
};
|
||||
|
||||
The name field should be set to something that is usefully descriptive
|
||||
for the board for configuration of supplies for other regulators and
|
||||
for use in logging and other diagnostic output. Normally the name
|
||||
used for the supply rail in the schematic is a good choice. If no
|
||||
name is provided then the subsystem will choose one.
|
||||
|
||||
Regulator-1 supplies power to Regulator-2. This relationship must be registered
|
||||
with the core so that Regulator-1 is also enabled when Consumer A enables its
|
||||
supply (Regulator-2). The supply regulator is set by the supply_regulator
|
||||
field below:-
|
||||
field below and co:-
|
||||
|
||||
static struct regulator_init_data regulator2_data = {
|
||||
.supply_regulator = "regulator_name",
|
||||
.supply_regulator = "Regulator-1",
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 2000000,
|
||||
|
@ -789,6 +789,16 @@ will behave normally, not taking the autosuspend delay into account.
|
||||
Similarly, if the power.use_autosuspend field isn't set then the autosuspend
|
||||
helper functions will behave just like the non-autosuspend counterparts.
|
||||
|
||||
Under some circumstances a driver or subsystem may want to prevent a device
|
||||
from autosuspending immediately, even though the usage counter is zero and the
|
||||
autosuspend delay time has expired. If the ->runtime_suspend() callback
|
||||
returns -EAGAIN or -EBUSY, and if the next autosuspend delay expiration time is
|
||||
in the future (as it normally would be if the callback invoked
|
||||
pm_runtime_mark_last_busy()), the PM core will automatically reschedule the
|
||||
autosuspend. The ->runtime_suspend() callback can't do this rescheduling
|
||||
itself because no suspend requests of any kind are accepted while the device is
|
||||
suspending (i.e., while the callback is running).
|
||||
|
||||
The implementation is well suited for asynchronous use in interrupt contexts.
|
||||
However such use inevitably involves races, because the PM core can't
|
||||
synchronize ->runtime_suspend() callbacks with the arrival of I/O requests.
|
||||
|
@ -144,7 +144,7 @@ and the default device ID in order to access the device on the active port.
|
||||
|
||||
After the host has completed enumeration of the entire network it releases
|
||||
devices by clearing device ID locks (calls rio_clear_locks()). For each endpoint
|
||||
in the system, it sets the Master Enable bit in the Port General Control CSR
|
||||
in the system, it sets the Discovered bit in the Port General Control CSR
|
||||
to indicate that enumeration is completed and agents are allowed to execute
|
||||
passive discovery of the network.
|
||||
|
||||
|
49
Documentation/rapidio/tsi721.txt
Normal file
49
Documentation/rapidio/tsi721.txt
Normal file
@ -0,0 +1,49 @@
|
||||
RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
|
||||
=========================================================================
|
||||
|
||||
I. Overview
|
||||
|
||||
This driver implements all currently defined RapidIO mport callback functions.
|
||||
It supports maintenance read and write operations, inbound and outbound RapidIO
|
||||
doorbells, inbound maintenance port-writes and RapidIO messaging.
|
||||
|
||||
To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
|
||||
channels. This mechanism provides access to larger range of hop counts and
|
||||
destination IDs without need for changes in outbound window translation.
|
||||
|
||||
RapidIO messaging support uses dedicated messaging channels for each mailbox.
|
||||
For inbound messages this driver uses destination ID matching to forward messages
|
||||
into the corresponding message queue. Messaging callbacks are implemented to be
|
||||
fully compatible with RIONET driver (Ethernet over RapidIO messaging services).
|
||||
|
||||
II. Known problems
|
||||
|
||||
None.
|
||||
|
||||
III. To do
|
||||
|
||||
Add DMA data transfers (non-messaging).
|
||||
Add inbound region (SRIO-to-PCIe) mapping.
|
||||
|
||||
IV. Version History
|
||||
|
||||
1.0.0 - Initial driver release.
|
||||
|
||||
V. License
|
||||
-----------------------------------------------
|
||||
|
||||
Copyright(c) 2011 Integrated Device Technology, Inc. All rights reserved.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
@ -20,8 +20,6 @@ Version: 1.2.14
|
||||
Date: 11/01/2001
|
||||
Historical Author: Andrew Manison <amanison@america.net>
|
||||
Primary Author: Doug McNash
|
||||
Support: support@computone.com
|
||||
Fixes and Updates: Mike Warfield <mhw@wittsend.com>
|
||||
|
||||
This file assumes that you are using the Computone drivers which are
|
||||
integrated into the kernel sources. For updating the drivers or installing
|
||||
|
@ -349,6 +349,7 @@ STAC92HD83*
|
||||
ref Reference board
|
||||
mic-ref Reference board with power management for ports
|
||||
dell-s14 Dell laptop
|
||||
dell-vostro-3500 Dell Vostro 3500 laptop
|
||||
hp HP laptops with (inverted) mute-LED
|
||||
hp-dv7-4000 HP dv-7 4000
|
||||
auto BIOS setup (default)
|
||||
|
@ -24,6 +24,7 @@ show up in /proc/sys/kernel:
|
||||
- bootloader_type [ X86 only ]
|
||||
- bootloader_version [ X86 only ]
|
||||
- callhome [ S390 only ]
|
||||
- cap_last_cap
|
||||
- core_pattern
|
||||
- core_pipe_limit
|
||||
- core_uses_pid
|
||||
@ -155,6 +156,13 @@ on has a service contract with IBM.
|
||||
|
||||
==============================================================
|
||||
|
||||
cap_last_cap
|
||||
|
||||
Highest valid capability of the running kernel. Exports
|
||||
CAP_LAST_CAP from the kernel.
|
||||
|
||||
==============================================================
|
||||
|
||||
core_pattern:
|
||||
|
||||
core_pattern is used to specify a core dumpfile pattern name.
|
||||
|
@ -379,10 +379,10 @@ EVENT_PROCESS:
|
||||
|
||||
# To closer match vmstat scanning statistics, only count isolate_both
|
||||
# and isolate_inactive as scanning. isolate_active is rotation
|
||||
# isolate_inactive == 0
|
||||
# isolate_active == 1
|
||||
# isolate_both == 2
|
||||
if ($isolate_mode != 1) {
|
||||
# isolate_inactive == 1
|
||||
# isolate_active == 2
|
||||
# isolate_both == 3
|
||||
if ($isolate_mode != 2) {
|
||||
$perprocesspid{$process_pid}->{HIGH_NR_SCANNED} += $nr_scanned;
|
||||
}
|
||||
$perprocesspid{$process_pid}->{HIGH_NR_CONTIG_DIRTY} += $nr_contig_dirty;
|
||||
|
File diff suppressed because it is too large
Load Diff
195
Documentation/watchdog/convert_drivers_to_kernel_api.txt
Normal file
195
Documentation/watchdog/convert_drivers_to_kernel_api.txt
Normal file
@ -0,0 +1,195 @@
|
||||
Converting old watchdog drivers to the watchdog framework
|
||||
by Wolfram Sang <w.sang@pengutronix.de>
|
||||
=========================================================
|
||||
|
||||
Before the watchdog framework came into the kernel, every driver had to
|
||||
implement the API on its own. Now, as the framework factored out the common
|
||||
components, those drivers can be lightened making it a user of the framework.
|
||||
This document shall guide you for this task. The necessary steps are described
|
||||
as well as things to look out for.
|
||||
|
||||
|
||||
Remove the file_operations struct
|
||||
---------------------------------
|
||||
|
||||
Old drivers define their own file_operations for actions like open(), write(),
|
||||
etc... These are now handled by the framework and just call the driver when
|
||||
needed. So, in general, the 'file_operations' struct and assorted functions can
|
||||
go. Only very few driver-specific details have to be moved to other functions.
|
||||
Here is a overview of the functions and probably needed actions:
|
||||
|
||||
- open: Everything dealing with resource management (file-open checks, magic
|
||||
close preparations) can simply go. Device specific stuff needs to go to the
|
||||
driver specific start-function. Note that for some drivers, the start-function
|
||||
also serves as the ping-function. If that is the case and you need start/stop
|
||||
to be balanced (clocks!), you are better off refactoring a separate start-function.
|
||||
|
||||
- close: Same hints as for open apply.
|
||||
|
||||
- write: Can simply go, all defined behaviour is taken care of by the framework,
|
||||
i.e. ping on write and magic char ('V') handling.
|
||||
|
||||
- ioctl: While the driver is allowed to have extensions to the IOCTL interface,
|
||||
the most common ones are handled by the framework, supported by some assistance
|
||||
from the driver:
|
||||
|
||||
WDIOC_GETSUPPORT:
|
||||
Returns the mandatory watchdog_info struct from the driver
|
||||
|
||||
WDIOC_GETSTATUS:
|
||||
Needs the status-callback defined, otherwise returns 0
|
||||
|
||||
WDIOC_GETBOOTSTATUS:
|
||||
Needs the bootstatus member properly set. Make sure it is 0 if you
|
||||
don't have further support!
|
||||
|
||||
WDIOC_SETOPTIONS:
|
||||
No preparations needed
|
||||
|
||||
WDIOC_KEEPALIVE:
|
||||
If wanted, options in watchdog_info need to have WDIOF_KEEPALIVEPING
|
||||
set
|
||||
|
||||
WDIOC_SETTIMEOUT:
|
||||
Options in watchdog_info need to have WDIOF_SETTIMEOUT set
|
||||
and a set_timeout-callback has to be defined. The core will also
|
||||
do limit-checking, if min_timeout and max_timeout in the watchdog
|
||||
device are set. All is optional.
|
||||
|
||||
WDIOC_GETTIMEOUT:
|
||||
No preparations needed
|
||||
|
||||
Other IOCTLs can be served using the ioctl-callback. Note that this is mainly
|
||||
intended for porting old drivers; new drivers should not invent private IOCTLs.
|
||||
Private IOCTLs are processed first. When the callback returns with
|
||||
-ENOIOCTLCMD, the IOCTLs of the framework will be tried, too. Any other error
|
||||
is directly given to the user.
|
||||
|
||||
Example conversion:
|
||||
|
||||
-static const struct file_operations s3c2410wdt_fops = {
|
||||
- .owner = THIS_MODULE,
|
||||
- .llseek = no_llseek,
|
||||
- .write = s3c2410wdt_write,
|
||||
- .unlocked_ioctl = s3c2410wdt_ioctl,
|
||||
- .open = s3c2410wdt_open,
|
||||
- .release = s3c2410wdt_release,
|
||||
-};
|
||||
|
||||
Check the functions for device-specific stuff and keep it for later
|
||||
refactoring. The rest can go.
|
||||
|
||||
|
||||
Remove the miscdevice
|
||||
---------------------
|
||||
|
||||
Since the file_operations are gone now, you can also remove the 'struct
|
||||
miscdevice'. The framework will create it on watchdog_dev_register() called by
|
||||
watchdog_register_device().
|
||||
|
||||
-static struct miscdevice s3c2410wdt_miscdev = {
|
||||
- .minor = WATCHDOG_MINOR,
|
||||
- .name = "watchdog",
|
||||
- .fops = &s3c2410wdt_fops,
|
||||
-};
|
||||
|
||||
|
||||
Remove obsolete includes and defines
|
||||
------------------------------------
|
||||
|
||||
Because of the simplifications, a few defines are probably unused now. Remove
|
||||
them. Includes can be removed, too. For example:
|
||||
|
||||
- #include <linux/fs.h>
|
||||
- #include <linux/miscdevice.h> (if MODULE_ALIAS_MISCDEV is not used)
|
||||
- #include <linux/uaccess.h> (if no custom IOCTLs are used)
|
||||
|
||||
|
||||
Add the watchdog operations
|
||||
---------------------------
|
||||
|
||||
All possible callbacks are defined in 'struct watchdog_ops'. You can find it
|
||||
explained in 'watchdog-kernel-api.txt' in this directory. start(), stop() and
|
||||
owner must be set, the rest are optional. You will easily find corresponding
|
||||
functions in the old driver. Note that you will now get a pointer to the
|
||||
watchdog_device as a parameter to these functions, so you probably have to
|
||||
change the function header. Other changes are most likely not needed, because
|
||||
here simply happens the direct hardware access. If you have device-specific
|
||||
code left from the above steps, it should be refactored into these callbacks.
|
||||
|
||||
Here is a simple example:
|
||||
|
||||
+static struct watchdog_ops s3c2410wdt_ops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .start = s3c2410wdt_start,
|
||||
+ .stop = s3c2410wdt_stop,
|
||||
+ .ping = s3c2410wdt_keepalive,
|
||||
+ .set_timeout = s3c2410wdt_set_heartbeat,
|
||||
+};
|
||||
|
||||
A typical function-header change looks like:
|
||||
|
||||
-static void s3c2410wdt_keepalive(void)
|
||||
+static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
|
||||
{
|
||||
...
|
||||
+
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
...
|
||||
|
||||
- s3c2410wdt_keepalive();
|
||||
+ s3c2410wdt_keepalive(&s3c2410_wdd);
|
||||
|
||||
|
||||
Add the watchdog device
|
||||
-----------------------
|
||||
|
||||
Now we need to create a 'struct watchdog_device' and populate it with the
|
||||
necessary information for the framework. The struct is also explained in detail
|
||||
in 'watchdog-kernel-api.txt' in this directory. We pass it the mandatory
|
||||
watchdog_info struct and the newly created watchdog_ops. Often, old drivers
|
||||
have their own record-keeping for things like bootstatus and timeout using
|
||||
static variables. Those have to be converted to use the members in
|
||||
watchdog_device. Note that the timeout values are unsigned int. Some drivers
|
||||
use signed int, so this has to be converted, too.
|
||||
|
||||
Here is a simple example for a watchdog device:
|
||||
|
||||
+static struct watchdog_device s3c2410_wdd = {
|
||||
+ .info = &s3c2410_wdt_ident,
|
||||
+ .ops = &s3c2410wdt_ops,
|
||||
+};
|
||||
|
||||
|
||||
Register the watchdog device
|
||||
----------------------------
|
||||
|
||||
Replace misc_register(&miscdev) with watchdog_register_device(&watchdog_dev).
|
||||
Make sure the return value gets checked and the error message, if present,
|
||||
still fits. Also convert the unregister case.
|
||||
|
||||
- ret = misc_register(&s3c2410wdt_miscdev);
|
||||
+ ret = watchdog_register_device(&s3c2410_wdd);
|
||||
|
||||
...
|
||||
|
||||
- misc_deregister(&s3c2410wdt_miscdev);
|
||||
+ watchdog_unregister_device(&s3c2410_wdd);
|
||||
|
||||
|
||||
Update the Kconfig-entry
|
||||
------------------------
|
||||
|
||||
The entry for the driver now needs to select WATCHDOG_CORE:
|
||||
|
||||
+ select WATCHDOG_CORE
|
||||
|
||||
|
||||
Create a patch and send it to upstream
|
||||
--------------------------------------
|
||||
|
||||
Make sure you understood Documentation/SubmittingPatches and send your patch to
|
||||
linux-watchdog@vger.kernel.org. We are looking forward to it :)
|
||||
|
10
Kbuild
10
Kbuild
@ -88,11 +88,13 @@ $(obj)/$(offsets-file): arch/$(SRCARCH)/kernel/asm-offsets.s Kbuild
|
||||
# 3) Check for missing system calls
|
||||
#
|
||||
|
||||
quiet_cmd_syscalls = CALL $<
|
||||
cmd_syscalls = $(CONFIG_SHELL) $< $(CC) $(c_flags)
|
||||
always += missing-syscalls
|
||||
targets += missing-syscalls
|
||||
|
||||
PHONY += missing-syscalls
|
||||
missing-syscalls: scripts/checksyscalls.sh FORCE
|
||||
quiet_cmd_syscalls = CALL $<
|
||||
cmd_syscalls = $(CONFIG_SHELL) $< $(CC) $(c_flags) $(missing_syscalls_flags)
|
||||
|
||||
missing-syscalls: scripts/checksyscalls.sh $(offsets-file) FORCE
|
||||
$(call cmd,syscalls)
|
||||
|
||||
# Keep these two files during make clean
|
||||
|
82
MAINTAINERS
82
MAINTAINERS
@ -316,6 +316,10 @@ W: http://wiki.analog.com/AD7879
|
||||
S: Supported
|
||||
F: drivers/input/touchscreen/ad7879.c
|
||||
|
||||
ADDRESS SPACE LAYOUT RANDOMIZATION (ASLR)
|
||||
M: Jiri Kosina <jkosina@suse.cz>
|
||||
S: Maintained
|
||||
|
||||
ADM1025 HARDWARE MONITOR DRIVER
|
||||
M: Jean Delvare <khali@linux-fr.org>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
@ -688,6 +692,12 @@ F: drivers/mtd/nand/bcm_umi_nand.c
|
||||
F: drivers/mtd/nand/bcm_umi_bch.c
|
||||
F: drivers/mtd/nand/nand_bcm_umi.h
|
||||
|
||||
ARM/CALXEDA HIGHBANK ARCHITECTURE
|
||||
M: Rob Herring <rob.herring@calxeda.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-highbank/
|
||||
|
||||
ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
|
||||
M: Anton Vorontsov <avorontsov@mvista.com>
|
||||
S: Maintained
|
||||
@ -787,6 +797,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-mx5/
|
||||
|
||||
ARM/FREESCALE IMX6
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
|
||||
F: arch/arm/mach-imx/*imx6*
|
||||
|
||||
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
@ -1015,6 +1032,7 @@ F: arch/arm/include/asm/hardware/ioc.h
|
||||
F: arch/arm/include/asm/hardware/iomd.h
|
||||
F: arch/arm/include/asm/hardware/memc.h
|
||||
F: arch/arm/mach-rpc/
|
||||
F: drivers/net/ethernet/8390/etherh.c
|
||||
F: drivers/net/ethernet/i825xx/ether1*
|
||||
F: drivers/net/ethernet/seeq/ether3*
|
||||
F: drivers/scsi/arm/
|
||||
@ -1088,6 +1106,7 @@ F: drivers/media/video/s5p-fimc/
|
||||
ARM/SAMSUNG S5P SERIES Multi Format Codec (MFC) SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
M: Kamil Debski <k.debski@samsung.com>
|
||||
M: Jeongtae Park <jtp.park@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org
|
||||
L: linux-media@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -1699,6 +1718,7 @@ F: include/linux/can.h
|
||||
F: include/linux/can/core.h
|
||||
F: include/linux/can/bcm.h
|
||||
F: include/linux/can/raw.h
|
||||
F: include/linux/can/gw.h
|
||||
|
||||
CAN NETWORK DRIVERS
|
||||
M: Wolfgang Grandegger <wg@grandegger.com>
|
||||
@ -2323,6 +2343,13 @@ S: Supported
|
||||
F: drivers/gpu/drm/i915
|
||||
F: include/drm/i915*
|
||||
|
||||
DRM DRIVERS FOR EXYNOS
|
||||
M: Inki Dae <inki.dae@samsung.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/exynos
|
||||
F: include/drm/exynos*
|
||||
|
||||
DSCC4 DRIVER
|
||||
M: Francois Romieu <romieu@fr.zoreil.com>
|
||||
L: netdev@vger.kernel.org
|
||||
@ -2369,7 +2396,7 @@ F: include/linux/netfilter_bridge/ebt_*.h
|
||||
F: net/bridge/netfilter/ebt*.c
|
||||
|
||||
ECRYPT FILE SYSTEM
|
||||
M: Tyler Hicks <tyhicks@linux.vnet.ibm.com>
|
||||
M: Tyler Hicks <tyhicks@canonical.com>
|
||||
M: Dustin Kirkland <kirkland@canonical.com>
|
||||
L: ecryptfs@vger.kernel.org
|
||||
W: https://launchpad.net/ecryptfs
|
||||
@ -2450,8 +2477,6 @@ L: linux-edac@vger.kernel.org
|
||||
W: bluesmoke.sourceforge.net
|
||||
S: Maintained
|
||||
F: drivers/edac/i7core_edac.c
|
||||
F: drivers/edac/edac_mce.c
|
||||
F: include/linux/edac_mce.h
|
||||
|
||||
EDAC-I82975X
|
||||
M: Ranganathan Desikan <ravi@jetztechnologies.com>
|
||||
@ -2475,6 +2500,13 @@ W: bluesmoke.sourceforge.net
|
||||
S: Maintained
|
||||
F: drivers/edac/r82600_edac.c
|
||||
|
||||
EDAC-SBRIDGE
|
||||
M: Mauro Carvalho Chehab <mchehab@redhat.com>
|
||||
L: linux-edac@vger.kernel.org
|
||||
W: bluesmoke.sourceforge.net
|
||||
S: Maintained
|
||||
F: drivers/edac/sb_edac.c
|
||||
|
||||
EDIROL UA-101/UA-1000 DRIVER
|
||||
M: Clemens Ladisch <clemens@ladisch.de>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
@ -2996,6 +3028,13 @@ F: Documentation/hw_random.txt
|
||||
F: drivers/char/hw_random/
|
||||
F: include/linux/hw_random.h
|
||||
|
||||
HARDWARE SPINLOCK CORE
|
||||
M: Ohad Ben-Cohen <ohad@wizery.com>
|
||||
S: Maintained
|
||||
F: Documentation/hwspinlock.txt
|
||||
F: drivers/hwspinlock/hwspinlock_*
|
||||
F: include/linux/hwspinlock.h
|
||||
|
||||
HARMONY SOUND DRIVER
|
||||
M: Kyle McMartin <kyle@mcmartin.ca>
|
||||
L: linux-parisc@vger.kernel.org
|
||||
@ -3188,8 +3227,7 @@ IA64 (Itanium) PLATFORM
|
||||
M: Tony Luck <tony.luck@intel.com>
|
||||
M: Fenghua Yu <fenghua.yu@intel.com>
|
||||
L: linux-ia64@vger.kernel.org
|
||||
W: http://www.ia64-linux.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux.git
|
||||
S: Maintained
|
||||
F: arch/ia64/
|
||||
|
||||
@ -3227,6 +3265,13 @@ F: Documentation/ide/
|
||||
F: drivers/ide/
|
||||
F: include/linux/ide.h
|
||||
|
||||
IDEAPAD LAPTOP EXTRAS DRIVER
|
||||
M: Ike Panhc <ike.pan@canonical.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
W: http://launchpad.net/ideapad-laptop
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/ideapad-laptop.c
|
||||
|
||||
IDE/ATAPI DRIVERS
|
||||
M: Borislav Petkov <petkovbb@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
@ -4013,6 +4058,7 @@ M: Eric Piel <eric.piel@tremplin-utc.net>
|
||||
S: Maintained
|
||||
F: Documentation/misc-devices/lis3lv02d
|
||||
F: drivers/misc/lis3lv02d/
|
||||
F: drivers/platform/x86/hp_accel.c
|
||||
|
||||
LLC (802.2)
|
||||
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
|
||||
@ -4440,11 +4486,9 @@ F: Documentation/networking/vxge.txt
|
||||
F: drivers/net/ethernet/neterion/
|
||||
|
||||
NETFILTER/IPTABLES/IPCHAINS
|
||||
P: Rusty Russell
|
||||
P: Marc Boucher
|
||||
P: James Morris
|
||||
P: Harald Welte
|
||||
P: Jozsef Kadlecsik
|
||||
M: Pablo Neira Ayuso <pablo@netfilter.org>
|
||||
M: Patrick McHardy <kaber@trash.net>
|
||||
L: netfilter-devel@vger.kernel.org
|
||||
L: netfilter@vger.kernel.org
|
||||
@ -4637,7 +4681,7 @@ L: linux-omap@vger.kernel.org
|
||||
W: http://www.muru.com/linux/omap/
|
||||
W: http://linux.omap.com/
|
||||
Q: http://patchwork.kernel.org/project/linux-omap/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
|
||||
S: Maintained
|
||||
F: arch/arm/*omap*/
|
||||
|
||||
@ -4685,6 +4729,13 @@ S: Maintained
|
||||
F: drivers/video/omap2/
|
||||
F: Documentation/arm/OMAP/DSS
|
||||
|
||||
OMAP HARDWARE SPINLOCK SUPPORT
|
||||
M: Ohad Ben-Cohen <ohad@wizery.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/hwspinlock/omap_hwspinlock.c
|
||||
F: arch/arm/mach-omap2/hwspinlock.c
|
||||
|
||||
OMAP MMC SUPPORT
|
||||
M: Jarkko Lavinen <jarkko.lavinen@nokia.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
@ -4967,7 +5018,7 @@ F: include/linux/i2c-algo-pca.h
|
||||
F: include/linux/i2c-pca-platform.h
|
||||
|
||||
PCI ERROR RECOVERY
|
||||
M: Linas Vepstas <linas@austin.ibm.com>
|
||||
M: Linas Vepstas <linasvepstas@gmail.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/PCI/pci-error-recovery.txt
|
||||
@ -5347,6 +5398,12 @@ F: fs/qnx4/
|
||||
F: include/linux/qnx4_fs.h
|
||||
F: include/linux/qnxtypes.h
|
||||
|
||||
QUALCOMM HEXAGON ARCHITECTURE
|
||||
M: Richard Kuo <rkuo@codeaurora.org>
|
||||
L: linux-hexagon@vger.kernel.org
|
||||
S: Supported
|
||||
F: arch/hexagon/
|
||||
|
||||
RADOS BLOCK DEVICE (RBD)
|
||||
F: include/linux/qnxtypes.h
|
||||
M: Yehuda Sadeh <yehuda@hq.newdream.net>
|
||||
@ -5422,7 +5479,7 @@ S: Maintained
|
||||
F: drivers/net/ethernet/rdc/r6040.c
|
||||
|
||||
RDS - RELIABLE DATAGRAM SOCKETS
|
||||
M: Andy Grover <andy.grover@oracle.com>
|
||||
M: Venkat Venkatsubra <venkat.x.venkatsubra@oracle.com>
|
||||
L: rds-devel@oss.oracle.com (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: net/rds/
|
||||
@ -6073,7 +6130,7 @@ F: sound/
|
||||
SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)
|
||||
M: Liam Girdwood <lrg@ti.com>
|
||||
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
W: http://alsa-project.org/main/index.php/ASoC
|
||||
S: Supported
|
||||
@ -6652,7 +6709,6 @@ F: drivers/net/ethernet/8390/ne-h8300.c
|
||||
|
||||
UDF FILESYSTEM
|
||||
M: Jan Kara <jack@suse.cz>
|
||||
W: http://linux-udf.sourceforge.net
|
||||
S: Maintained
|
||||
F: Documentation/filesystems/udf.txt
|
||||
F: fs/udf/
|
||||
|
10
Makefile
10
Makefile
@ -1,8 +1,8 @@
|
||||
VERSION = 3
|
||||
PATCHLEVEL = 1
|
||||
PATCHLEVEL = 2
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION =
|
||||
NAME = "Divemaster Edition"
|
||||
EXTRAVERSION = -rc2
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
@ -983,7 +983,6 @@ archprepare: prepare1 scripts_basic
|
||||
|
||||
prepare0: archprepare FORCE
|
||||
$(Q)$(MAKE) $(build)=.
|
||||
$(Q)$(MAKE) $(build)=. missing-syscalls
|
||||
|
||||
# All the preparing..
|
||||
prepare: prepare0
|
||||
@ -1198,7 +1197,7 @@ distclean: mrproper
|
||||
@find $(srctree) $(RCS_FIND_IGNORE) \
|
||||
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
|
||||
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
|
||||
-o -name '.*.rej' -o -size 0 \
|
||||
-o -name '.*.rej' \
|
||||
-o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
|
||||
-type f -print | xargs rm -f
|
||||
|
||||
@ -1296,7 +1295,6 @@ help:
|
||||
@echo ' 2: warnings which occur quite often but may still be relevant'
|
||||
@echo ' 3: more obscure warnings, can most likely be ignored'
|
||||
@echo ' Multiple levels can be combined with W=12 or W=123'
|
||||
@echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections'
|
||||
@echo ''
|
||||
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
|
||||
@echo 'For further info see the ./README file'
|
||||
|
@ -445,11 +445,6 @@ config ALPHA_EV67
|
||||
Is this a machine based on the EV67 core? If in doubt, select N here
|
||||
and the machine will be treated as an EV6.
|
||||
|
||||
config ALPHA_EV7
|
||||
bool
|
||||
depends on ALPHA_MARVEL
|
||||
default y
|
||||
|
||||
config ALPHA_MCPCIA
|
||||
bool
|
||||
depends on ALPHA_RAWHIDE
|
||||
|
@ -457,10 +457,12 @@
|
||||
#define __NR_clock_adjtime 499
|
||||
#define __NR_syncfs 500
|
||||
#define __NR_setns 501
|
||||
#define __NR_accept4 502
|
||||
#define __NR_sendmmsg 503
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define NR_SYSCALLS 502
|
||||
#define NR_SYSCALLS 504
|
||||
|
||||
#define __ARCH_WANT_IPC_PARSE_VERSION
|
||||
#define __ARCH_WANT_OLD_READDIR
|
||||
|
@ -303,6 +303,7 @@ irongate_init_arch(void)
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/agp_backend.h>
|
||||
#include <linux/agpgart.h>
|
||||
#include <linux/export.h>
|
||||
#include <asm/pgalloc.h>
|
||||
|
||||
#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
|
||||
|
@ -10,6 +10,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/stat.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
|
@ -7,6 +7,7 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
@ -43,6 +43,7 @@
|
||||
#include <asm/setup.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
extern struct atomic_notifier_head panic_notifier_list;
|
||||
static int alpha_panic_event(struct notifier_block *, unsigned long, void *);
|
||||
|
@ -520,6 +520,8 @@ sys_call_table:
|
||||
.quad sys_clock_adjtime
|
||||
.quad sys_syncfs /* 500 */
|
||||
.quad sys_setns
|
||||
.quad sys_accept4
|
||||
.quad sys_sendmmsg
|
||||
|
||||
.size sys_call_table, . - sys_call_table
|
||||
.type sys_call_table, @object
|
||||
|
@ -334,6 +334,20 @@ config ARCH_BCMRING
|
||||
help
|
||||
Support for Broadcom's BCMRing platform.
|
||||
|
||||
config ARCH_HIGHBANK
|
||||
bool "Calxeda Highbank-based"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select ARM_TIMER_SP804
|
||||
select CLKDEV_LOOKUP
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_ARM_SCU
|
||||
select USE_OF
|
||||
help
|
||||
Support for the Calxeda Highbank SoC based boards.
|
||||
|
||||
config ARCH_CLPS711X
|
||||
bool "Cirrus Logic CLPS711x/EP721x-based"
|
||||
select CPU_ARM720T
|
||||
@ -394,7 +408,7 @@ config ARCH_EP93XX
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select NEED_MEMORY_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
This enables support for the Cirrus EP93xx series of CPUs.
|
||||
|
||||
@ -417,6 +431,7 @@ config ARCH_MXC
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select HAVE_SCHED_CLOCK
|
||||
select MULTI_IRQ_HANDLER
|
||||
help
|
||||
Support for Freescale MXC/iMX-based family of processors
|
||||
|
||||
@ -580,6 +595,7 @@ config ARCH_MMP
|
||||
select TICK_ONESHOT
|
||||
select PLAT_PXA
|
||||
select SPARSE_IRQ
|
||||
select GENERIC_ALLOCATOR
|
||||
help
|
||||
Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
|
||||
|
||||
@ -609,14 +625,6 @@ config ARCH_W90X900
|
||||
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
|
||||
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
|
||||
|
||||
config ARCH_NUC93X
|
||||
bool "Nuvoton NUC93X CPU"
|
||||
select CPU_ARM926T
|
||||
select CLKDEV_LOOKUP
|
||||
help
|
||||
Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
|
||||
low-power and high performance MPEG-4/JPEG multimedia controller chip.
|
||||
|
||||
config ARCH_TEGRA
|
||||
bool "NVIDIA Tegra"
|
||||
select CLKDEV_LOOKUP
|
||||
@ -630,6 +638,24 @@ config ARCH_TEGRA
|
||||
This enables support for NVIDIA Tegra based systems (Tegra APX,
|
||||
Tegra 6xx and Tegra 2 series).
|
||||
|
||||
config ARCH_PICOXCELL
|
||||
bool "Picochip picoXcell"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
select ARM_VIC
|
||||
select CPU_V6K
|
||||
select DW_APB_TIMER
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select HAVE_SCHED_CLOCK
|
||||
select HAVE_TCM
|
||||
select NO_IOPORT
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for systems based on the Picochip picoXcell
|
||||
family of Femtocell devices. The picoxcell support requires device tree
|
||||
for all boards.
|
||||
|
||||
config ARCH_PNX4008
|
||||
bool "Philips Nexperia PNX4008 Mobile"
|
||||
select CPU_ARM926T
|
||||
@ -744,6 +770,7 @@ config ARCH_S3C64XX
|
||||
select CPU_V6
|
||||
select ARM_VIC
|
||||
select HAVE_CLK
|
||||
select HAVE_TCM
|
||||
select CLKDEV_LOOKUP
|
||||
select NO_IOPORT
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
@ -752,9 +779,6 @@ config ARCH_S3C64XX
|
||||
select SAMSUNG_CLKSRC
|
||||
select SAMSUNG_IRQ_VIC_TIMER
|
||||
select S3C_GPIO_TRACK
|
||||
select S3C_GPIO_PULL_UPDOWN
|
||||
select S3C_GPIO_CFG_S3C24XX
|
||||
select S3C_GPIO_CFG_S3C64XX
|
||||
select S3C_DEV_NAND
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select SAMSUNG_GPIOLIB_4BIT
|
||||
@ -813,8 +837,8 @@ config ARCH_S5PV210
|
||||
help
|
||||
Samsung S5PV210/S5PC110 series based systems
|
||||
|
||||
config ARCH_EXYNOS4
|
||||
bool "Samsung EXYNOS4"
|
||||
config ARCH_EXYNOS
|
||||
bool "SAMSUNG EXYNOS"
|
||||
select CPU_V7
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
@ -828,7 +852,7 @@ config ARCH_EXYNOS4
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Samsung EXYNOS4 series based systems
|
||||
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
|
||||
|
||||
config ARCH_SHARK
|
||||
bool "Shark"
|
||||
@ -861,6 +885,7 @@ config ARCH_U300
|
||||
select HAVE_SCHED_CLOCK
|
||||
select HAVE_TCM
|
||||
select ARM_AMBA
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
select ARM_VIC
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select CLKDEV_LOOKUP
|
||||
@ -1011,8 +1036,6 @@ source "arch/arm/mach-netx/Kconfig"
|
||||
source "arch/arm/mach-nomadik/Kconfig"
|
||||
source "arch/arm/plat-nomadik/Kconfig"
|
||||
|
||||
source "arch/arm/mach-nuc93x/Kconfig"
|
||||
|
||||
source "arch/arm/plat-omap/Kconfig"
|
||||
|
||||
source "arch/arm/mach-omap1/Kconfig"
|
||||
@ -1056,7 +1079,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
|
||||
|
||||
source "arch/arm/mach-s5pv210/Kconfig"
|
||||
|
||||
source "arch/arm/mach-exynos4/Kconfig"
|
||||
source "arch/arm/mach-exynos/Kconfig"
|
||||
|
||||
source "arch/arm/mach-shmobile/Kconfig"
|
||||
|
||||
@ -1406,7 +1429,7 @@ config SMP
|
||||
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
|
||||
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
|
||||
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
|
||||
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
|
||||
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
|
||||
depends on MMU
|
||||
select USE_GENERIC_SMP_HELPERS
|
||||
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
|
||||
@ -2044,6 +2067,7 @@ config CPU_FREQ_PXA
|
||||
bool
|
||||
depends on CPU_FREQ && ARCH_PXA && PXA25x
|
||||
default y
|
||||
select CPU_FREQ_TABLE
|
||||
select CPU_FREQ_DEFAULT_GOV_USERSPACE
|
||||
|
||||
config CPU_FREQ_S3C
|
||||
@ -2187,7 +2211,7 @@ menu "Power management options"
|
||||
source "kernel/power/Kconfig"
|
||||
|
||||
config ARCH_SUSPEND_POSSIBLE
|
||||
depends on !ARCH_S5P64X0 && !ARCH_S5PC100
|
||||
depends on !ARCH_S5PC100
|
||||
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
|
||||
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
|
||||
def_bool y
|
||||
|
@ -128,6 +128,125 @@ choice
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the second serial port on these devices.
|
||||
|
||||
config DEBUG_HIGHBANK_UART
|
||||
bool "Kernel low-level debugging messages via Highbank UART"
|
||||
depends on ARCH_HIGHBANK
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the UART on Highbank based devices.
|
||||
|
||||
config DEBUG_IMX1_UART
|
||||
bool "i.MX1 Debug UART"
|
||||
depends on SOC_IMX1
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX1.
|
||||
|
||||
config DEBUG_IMX23_UART
|
||||
bool "i.MX23 Debug UART"
|
||||
depends on SOC_IMX23
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX23.
|
||||
|
||||
config DEBUG_IMX25_UART
|
||||
bool "i.MX25 Debug UART"
|
||||
depends on SOC_IMX25
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX25.
|
||||
|
||||
config DEBUG_IMX21_IMX27_UART
|
||||
bool "i.MX21 and i.MX27 Debug UART"
|
||||
depends on SOC_IMX21 || SOC_IMX27
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX21 or i.MX27.
|
||||
|
||||
config DEBUG_IMX28_UART
|
||||
bool "i.MX28 Debug UART"
|
||||
depends on SOC_IMX28
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX28.
|
||||
|
||||
config DEBUG_IMX31_IMX35_UART
|
||||
bool "i.MX31 and i.MX35 Debug UART"
|
||||
depends on SOC_IMX31 || SOC_IMX35
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX31 or i.MX35.
|
||||
|
||||
config DEBUG_IMX51_UART
|
||||
bool "i.MX51 Debug UART"
|
||||
depends on SOC_IMX51
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX51.
|
||||
|
||||
config DEBUG_IMX50_IMX53_UART
|
||||
bool "i.MX50 and i.MX53 Debug UART"
|
||||
depends on SOC_IMX50 || SOC_IMX53
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX50 or i.MX53.
|
||||
|
||||
config DEBUG_IMX6Q_UART
|
||||
bool "i.MX6Q Debug UART"
|
||||
depends on SOC_IMX6Q
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX6Q.
|
||||
|
||||
config DEBUG_S3C_UART0
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 0 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 0. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART1
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 1 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 1. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART2
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 2 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 2. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_REALVIEW_STD_PORT
|
||||
bool "RealView Default UART"
|
||||
depends on ARCH_REALVIEW
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on RealView EB, PB11MP, PBA8
|
||||
and PBX platforms.
|
||||
|
||||
config DEBUG_REALVIEW_PB1176_PORT
|
||||
bool "RealView PB1176 UART"
|
||||
depends on MACH_REALVIEW_PB1176
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the standard serial port on the RealView
|
||||
PB1176 platform.
|
||||
|
||||
endchoice
|
||||
|
||||
config EARLY_PRINTK
|
||||
@ -146,18 +265,6 @@ config OC_ETM
|
||||
buffer driver that will allow you to collect traces of the
|
||||
kernel code.
|
||||
|
||||
config DEBUG_S3C_UART
|
||||
depends on PLAT_SAMSUNG
|
||||
int "S3C UART to use for low-level debug"
|
||||
default "0"
|
||||
help
|
||||
Choice for UART for kernel low-level using S3C UARTS,
|
||||
should be between zero and two. The port must have been
|
||||
initialised by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config ARM_KPROBES_TEST
|
||||
tristate "Kprobes test module"
|
||||
depends on KPROBES && MODULES
|
||||
|
@ -144,6 +144,7 @@ machine-$(CONFIG_ARCH_EBSA110) := ebsa110
|
||||
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
|
||||
machine-$(CONFIG_ARCH_GEMINI) := gemini
|
||||
machine-$(CONFIG_ARCH_H720X) := h720x
|
||||
machine-$(CONFIG_ARCH_HIGHBANK) := highbank
|
||||
machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
|
||||
machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
|
||||
machine-$(CONFIG_ARCH_IOP32X) := iop32x
|
||||
@ -157,10 +158,8 @@ machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
|
||||
machine-$(CONFIG_ARCH_MMP) := mmp
|
||||
machine-$(CONFIG_ARCH_MSM) := msm
|
||||
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
|
||||
machine-$(CONFIG_ARCH_MX1) := imx
|
||||
machine-$(CONFIG_ARCH_MX2) := imx
|
||||
machine-$(CONFIG_ARCH_MX25) := imx
|
||||
machine-$(CONFIG_ARCH_MX3) := imx
|
||||
machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
|
||||
machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
|
||||
machine-$(CONFIG_ARCH_MX5) := mx5
|
||||
machine-$(CONFIG_ARCH_MXS) := mxs
|
||||
machine-$(CONFIG_ARCH_NETX) := netx
|
||||
@ -170,6 +169,7 @@ machine-$(CONFIG_ARCH_OMAP2) := omap2
|
||||
machine-$(CONFIG_ARCH_OMAP3) := omap2
|
||||
machine-$(CONFIG_ARCH_OMAP4) := omap2
|
||||
machine-$(CONFIG_ARCH_ORION5X) := orion5x
|
||||
machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
|
||||
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
|
||||
machine-$(CONFIG_ARCH_PRIMA2) := prima2
|
||||
machine-$(CONFIG_ARCH_PXA) := pxa
|
||||
@ -180,7 +180,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
|
||||
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
|
||||
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
|
||||
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
|
||||
machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
|
||||
machine-$(CONFIG_ARCH_EXYNOS4) := exynos
|
||||
machine-$(CONFIG_ARCH_SA1100) := sa1100
|
||||
machine-$(CONFIG_ARCH_SHARK) := shark
|
||||
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
|
||||
@ -192,7 +192,6 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile
|
||||
machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
|
||||
machine-$(CONFIG_ARCH_VT8500) := vt8500
|
||||
machine-$(CONFIG_ARCH_W90X900) := w90x900
|
||||
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
|
||||
machine-$(CONFIG_FOOTBRIDGE) := footbridge
|
||||
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
|
||||
|
119
arch/arm/boot/dts/at91sam9g20.dtsi
Normal file
119
arch/arm/boot/dts/at91sam9g20.dtsi
Normal file
@ -0,0 +1,119 @@
|
||||
/*
|
||||
* at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
|
||||
*
|
||||
* Copyright (C) 2011 Atmel,
|
||||
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
|
||||
* 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G20 family SoC";
|
||||
compatible = "atmel,at91sam9g20";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
||||
serial5 = &usart4;
|
||||
serial6 = &usart5;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
};
|
||||
};
|
||||
|
||||
memory@20000000 {
|
||||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
interrupt-parent;
|
||||
reg = <0xfffff000 0x200>;
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffb0000 0x200>;
|
||||
interrupts = <6>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffb4000 0x200>;
|
||||
interrupts = <7>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffb8000 0x200>;
|
||||
interrupts = <8>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@fffd0000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffd0000 0x200>;
|
||||
interrupts = <23>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart4: serial@fffd4000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffd4000 0x200>;
|
||||
interrupts = <24>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart5: serial@fffd8000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffd8000 0x200>;
|
||||
interrupts = <25>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
106
arch/arm/boot/dts/at91sam9g45.dtsi
Normal file
106
arch/arm/boot/dts/at91sam9g45.dtsi
Normal file
@ -0,0 +1,106 @@
|
||||
/*
|
||||
* at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
|
||||
* applies to AT91SAM9G45, AT91SAM9M10,
|
||||
* AT91SAM9G46, AT91SAM9M11 SoC
|
||||
*
|
||||
* Copyright (C) 2011 Atmel,
|
||||
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G45 family SoC";
|
||||
compatible = "atmel,at91sam9g45";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
};
|
||||
};
|
||||
|
||||
memory@70000000 {
|
||||
reg = <0x70000000 0x10000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
interrupt-parent;
|
||||
reg = <0xfffff000 0x200>;
|
||||
};
|
||||
|
||||
dma: dma-controller@ffffec00 {
|
||||
compatible = "atmel,at91sam9g45-dma";
|
||||
reg = <0xffffec00 0x200>;
|
||||
interrupts = <21>;
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@fff8c000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff8c000 0x200>;
|
||||
interrupts = <7>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@fff90000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff90000 0x200>;
|
||||
interrupts = <8>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@fff94000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff94000 0x200>;
|
||||
interrupts = <9>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@fff98000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff98000 0x200>;
|
||||
interrupts = <10>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
35
arch/arm/boot/dts/at91sam9m10g45ek.dts
Normal file
35
arch/arm/boot/dts/at91sam9m10g45ek.dts
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
|
||||
*
|
||||
* Copyright (C) 2011 Atmel,
|
||||
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9g45.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9M10G45-EK";
|
||||
compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
|
||||
};
|
||||
|
||||
memory@70000000 {
|
||||
reg = <0x70000000 0x4000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@ffffee00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fff90000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
198
arch/arm/boot/dts/highbank.dts
Normal file
198
arch/arm/boot/dts/highbank.dts
Normal file
@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Copyright 2011 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/* First 4KB has pen for secondary cores. */
|
||||
/memreserve/ 0x00000000 0x0001000;
|
||||
|
||||
/ {
|
||||
model = "Calxeda Highbank";
|
||||
compatible = "calxeda,highbank";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0xff900000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyAMA0";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
timer@fff10600 {
|
||||
compatible = "arm,smp-twd";
|
||||
reg = <0xfff10600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
watchdog@fff10620 {
|
||||
compatible = "arm,cortex-a9-wdt";
|
||||
reg = <0xfff10620 0x20>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
<0xfff10100 0x100>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
interrupts = <0 70 4>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
|
||||
};
|
||||
|
||||
sata@ffe08000 {
|
||||
compatible = "calxeda,hb-ahci";
|
||||
reg = <0xffe08000 0x10000>;
|
||||
interrupts = <0 83 4>;
|
||||
};
|
||||
|
||||
sdhci@ffe0e000 {
|
||||
compatible = "calxeda,hb-sdhci";
|
||||
reg = <0xffe0e000 0x1000>;
|
||||
interrupts = <0 90 4>;
|
||||
};
|
||||
|
||||
ipc@fff20000 {
|
||||
compatible = "arm,pl320", "arm,primecell";
|
||||
reg = <0xfff20000 0x1000>;
|
||||
interrupts = <0 7 4>;
|
||||
};
|
||||
|
||||
gpioe: gpio@fff30000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff30000 0x1000>;
|
||||
interrupts = <0 14 4>;
|
||||
};
|
||||
|
||||
gpiof: gpio@fff31000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff31000 0x1000>;
|
||||
interrupts = <0 15 4>;
|
||||
};
|
||||
|
||||
gpiog: gpio@fff32000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff32000 0x1000>;
|
||||
interrupts = <0 16 4>;
|
||||
};
|
||||
|
||||
gpioh: gpio@fff33000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff33000 0x1000>;
|
||||
interrupts = <0 17 4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0xfff34000 0x1000>;
|
||||
interrupts = <0 18 4>;
|
||||
};
|
||||
|
||||
rtc@fff35000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0xfff35000 0x1000>;
|
||||
interrupts = <0 19 4>;
|
||||
};
|
||||
|
||||
serial@fff36000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xfff36000 0x1000>;
|
||||
interrupts = <0 20 4>;
|
||||
};
|
||||
|
||||
smic@fff3a000 {
|
||||
compatible = "ipmi-smic";
|
||||
device_type = "ipmi";
|
||||
reg = <0xfff3a000 0x1000>;
|
||||
interrupts = <0 24 4>;
|
||||
reg-size = <4>;
|
||||
reg-spacing = <4>;
|
||||
};
|
||||
|
||||
sregs@fff3c000 {
|
||||
compatible = "calxeda,hb-sregs";
|
||||
reg = <0xfff3c000 0x1000>;
|
||||
};
|
||||
|
||||
dma@fff3d000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0xfff3d000 0x1000>;
|
||||
interrupts = <0 92 4>;
|
||||
};
|
||||
};
|
||||
};
|
135
arch/arm/boot/dts/imx51-babbage.dts
Normal file
135
arch/arm/boot/dts/imx51-babbage.dts
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX51 Babbage Board";
|
||||
compatible = "fsl,imx51-babbage", "fsl,imx51";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x90000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips@70000000 { /* aips-1 */
|
||||
spba@70000000 {
|
||||
esdhc@70004000 { /* ESDHC1 */
|
||||
fsl,cd-internal;
|
||||
fsl,wp-internal;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@70008000 { /* ESDHC2 */
|
||||
cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
|
||||
wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart2: uart@7000c000 { /* UART3 */
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@70010000 { /* ECSPI1 */
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
|
||||
<&gpio3 25 0>; /* GPIO4_25 */
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mc13892";
|
||||
spi-max-frequency = <6000000>;
|
||||
reg = <0>;
|
||||
mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
|
||||
fsl,mc13xxx-uses-regulator;
|
||||
};
|
||||
|
||||
flash: at45db321d@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "Kernel";
|
||||
reg = <0x40000 0x3c0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wdog@73f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc-babbage";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
};
|
||||
|
||||
uart0: uart@73fbc000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: uart@73fc0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* aips-2 */
|
||||
sdma@83fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
i2c@83fc4000 { /* I2C2 */
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
};
|
||||
|
||||
fec@83fec000 {
|
||||
phy-mode = "mii";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio1 21 0>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
246
arch/arm/boot/dts/imx51.dtsi
Normal file
246
arch/arm/boot/dts/imx51.dtsi
Normal file
@ -0,0 +1,246 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@e0000000 {
|
||||
compatible = "fsl,imx51-tzic", "fsl,tzic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xe0000000 0x4000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
aips@70000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x70000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
spba@70000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x70000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
esdhc@70004000 { /* ESDHC1 */
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc@70008000 { /* ESDHC2 */
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@7000c000 { /* UART3 */
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x7000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@70010000 { /* ECSPI1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x70010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc@70020000 { /* ESDHC3 */
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc@70024000 { /* ESDHC4 */
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@73f84000 { /* GPIO1 */
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x73f84000 0x4000>;
|
||||
interrupts = <50 51>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio1: gpio@73f88000 { /* GPIO2 */
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x73f88000 0x4000>;
|
||||
interrupts = <52 53>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio2: gpio@73f8c000 { /* GPIO3 */
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x73f8c000 0x4000>;
|
||||
interrupts = <54 55>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio3: gpio@73f90000 { /* GPIO4 */
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x73f90000 0x4000>;
|
||||
interrupts = <56 57>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
wdog@73f98000 { /* WDOG1 */
|
||||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@73f9c000 { /* WDOG2 */
|
||||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@73fbc000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@73fc0000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
ecspi@83fac000 { /* ECSPI2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x83fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma@83fb0000 {
|
||||
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x83fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
|
||||
cspi@83fc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x83fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@83fc4000 { /* I2C2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x83fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@83fc8000 { /* I2C1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x83fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec@83fec000 {
|
||||
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
|
||||
reg = <0x83fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
113
arch/arm/boot/dts/imx53-ard.dts
Normal file
113
arch/arm/boot/dts/imx53-ard.dts
Normal file
@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Automotive Reference Design Board";
|
||||
compatible = "fsl,imx53-ard", "fsl,imx53";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
|
||||
wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-ard";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
uart0: uart@53fbc000 { /* UART1 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eim-cs1@f4000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eim-bus", "simple-bus";
|
||||
reg = <0xf4000000 0x3ff0000>;
|
||||
ranges;
|
||||
|
||||
lan9220@f4000000 {
|
||||
compatible = "smsc,lan9220", "smsc,lan9115";
|
||||
reg = <0xf4000000 0x2000000>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <31>;
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-push-pull;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
home {
|
||||
label = "Home";
|
||||
gpios = <&gpio4 10 0>; /* GPIO5_10 */
|
||||
linux,code = <102>; /* KEY_HOME */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpio4 11 0>; /* GPIO5_11 */
|
||||
linux,code = <158>; /* KEY_BACK */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
program {
|
||||
label = "Program";
|
||||
gpios = <&gpio4 12 0>; /* GPIO5_12 */
|
||||
linux,code = <362>; /* KEY_PROGRAM */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio4 13 0>; /* GPIO5_13 */
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio3 0 0>; /* GPIO4_0 */
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
};
|
120
arch/arm/boot/dts/imx53-evk.dts
Normal file
120
arch/arm/boot/dts/imx53-evk.dts
Normal file
@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Evaluation Kit";
|
||||
compatible = "fsl,imx53-evk", "fsl,imx53";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x80000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
|
||||
wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
|
||||
<&gpio2 19 0>; /* GPIO3_19 */
|
||||
status = "okay";
|
||||
|
||||
flash: at45db321d@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "Kernel";
|
||||
reg = <0x40000 0x3c0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
|
||||
wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-evk";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
uart0: uart@53fbc000 { /* UART1 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@08 {
|
||||
compatible = "fsl,mc13892", "fsl,mc13xxx";
|
||||
reg = <0x08>;
|
||||
};
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
};
|
||||
|
||||
fec@63fec000 {
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
green {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio6 7 0>; /* GPIO7_7 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
125
arch/arm/boot/dts/imx53-qsb.dts
Normal file
125
arch/arm/boot/dts/imx53-qsb.dts
Normal file
@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Quick Start Board";
|
||||
compatible = "fsl,imx53-qsb", "fsl,imx53";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
|
||||
wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-qsb";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
uart0: uart@53fbc000 { /* UART1 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
compatible = "fsl,mma8450";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
pmic: dialog@48 {
|
||||
compatible = "dialog,da9053", "dialog,da9052";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
fec@63fec000 {
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio0 8 0>; /* GPIO1_8 */
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 14 0>; /* GPIO2_14 */
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 15 0>; /* GPIO2_15 */
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio6 7 0>; /* GPIO7_7 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
169
arch/arm/boot/dts/imx53-smd.dts
Normal file
169
arch/arm/boot/dts/imx53-smd.dts
Normal file
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
|
||||
compatible = "fsl,imx53-smd", "fsl,imx53";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
|
||||
wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@50008000 { /* ESDHC2 */
|
||||
fsl,card-wired;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart2: uart@5000c000 { /* UART3 */
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
|
||||
<&gpio2 19 0>; /* GPIO3_19 */
|
||||
status = "okay";
|
||||
|
||||
zigbee: mc1323@0 {
|
||||
compatible = "fsl,mc1323";
|
||||
spi-max-frequency = <8000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
flash: m25p32@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32", "st,m25p";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "Kernel";
|
||||
reg = <0x40000 0x3c0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
fsl,card-wired;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-smd";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
uart0: uart@53fbc000 { /* UART1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: uart@53fc0000 { /* UART2 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
|
||||
magnetometer: mag3110@0e {
|
||||
compatible = "fsl,mag3110";
|
||||
reg = <0x0e>;
|
||||
};
|
||||
|
||||
touchkey: mpr121@5a {
|
||||
compatible = "fsl,mpr121";
|
||||
reg = <0x5a>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
compatible = "fsl,mma8450";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
camera: ov5642@3c {
|
||||
compatible = "ovti,ov5642";
|
||||
reg = <0x3c>;
|
||||
};
|
||||
|
||||
pmic: dialog@48 {
|
||||
compatible = "dialog,da9053", "dialog,da9052";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
fec@63fec000 {
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 14 0>; /* GPIO2_14 */
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 15 0>; /* GPIO2_15 */
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
};
|
301
arch/arm/boot/dts/imx53.dtsi
Normal file
301
arch/arm/boot/dts/imx53.dtsi
Normal file
@ -0,0 +1,301 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@0fffc000 {
|
||||
compatible = "fsl,imx53-tzic", "fsl,tzic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x0fffc000 0x4000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x50000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
spba@50000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x50000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc@50008000 { /* ESDHC2 */
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@5000c000 { /* UART3 */
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x5000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x50010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc@50024000 { /* ESDHC4 */
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@53f84000 { /* GPIO1 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53f84000 0x4000>;
|
||||
interrupts = <50 51>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio1: gpio@53f88000 { /* GPIO2 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53f88000 0x4000>;
|
||||
interrupts = <52 53>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio2: gpio@53f8c000 { /* GPIO3 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53f8c000 0x4000>;
|
||||
interrupts = <54 55>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio3: gpio@53f90000 { /* GPIO4 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53f90000 0x4000>;
|
||||
interrupts = <56 57>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@53f9c000 { /* WDOG2 */
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@53fbc000 { /* UART1 */
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@53fc0000 { /* UART2 */
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio4: gpio@53fdc000 { /* GPIO5 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
interrupts = <103 104>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@53fe0000 { /* GPIO6 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53fe0000 0x4000>;
|
||||
interrupts = <105 106>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio6: gpio@53fe4000 { /* GPIO7 */
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53fe4000 0x4000>;
|
||||
interrupts = <107 108>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
i2c@53fec000 { /* I2C3 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x53fec000 0x4000>;
|
||||
interrupts = <64>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@53ff0000 { /* UART4 */
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53ff0000 0x4000>;
|
||||
interrupts = <13>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x60000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
uart4: uart@63f90000 { /* UART5 */
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x63f90000 0x4000>;
|
||||
interrupts = <86>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@63fac000 { /* ECSPI2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x63fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma@63fb0000 {
|
||||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
|
||||
cspi@63fc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x63fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x63fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x63fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec@63fec000 {
|
||||
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||||
reg = <0x63fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
62
arch/arm/boot/dts/imx6q-sabreauto.dts
Normal file
62
arch/arm/boot/dts/imx6q-sabreauto.dts
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad SABRE Automotive Board";
|
||||
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
enet@02188000 {
|
||||
phy-mode = "rgmii";
|
||||
local-mac-address = [00 04 9F 01 1B 61];
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
|
||||
wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
fsl,card-wired;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: uart@021f0000 { /* UART4 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
debug-led {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio2 25 0>; /* GPIO3_25 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
575
arch/arm/boot/dts/imx6q.dtsi
Normal file
575
arch/arm/boot/dts/imx6q.dtsi
Normal file
@ -0,0 +1,575 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
timer@00a00600 {
|
||||
compatible = "arm,smp-twd";
|
||||
reg = <0x00a00600 0x100>;
|
||||
interrupts = <1 13 0xf4>;
|
||||
};
|
||||
|
||||
L2: l2-cache@00a02000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x00a02000 0x1000>;
|
||||
interrupts = <0 92 0x04>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x100000>;
|
||||
ranges;
|
||||
|
||||
spba-bus@02000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
spdif@02004000 {
|
||||
reg = <0x02004000 0x4000>;
|
||||
interrupts = <0 52 0x04>;
|
||||
};
|
||||
|
||||
ecspi@02008000 { /* eCSPI1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@0200c000 { /* eCSPI2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@02010000 { /* eCSPI3 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@02014000 { /* eCSPI4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@02018000 { /* eCSPI5 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 35 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@02020000 { /* UART1 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esai@02024000 {
|
||||
reg = <0x02024000 0x4000>;
|
||||
interrupts = <0 51 0x04>;
|
||||
};
|
||||
|
||||
ssi@02028000 { /* SSI1 */
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
};
|
||||
|
||||
ssi@0202c000 { /* SSI2 */
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
};
|
||||
|
||||
ssi@02030000 { /* SSI3 */
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
};
|
||||
|
||||
asrc@02034000 {
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <0 50 0x04>;
|
||||
};
|
||||
|
||||
spba@0203c000 {
|
||||
reg = <0x0203c000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
vpu@02040000 {
|
||||
reg = <0x02040000 0x3c000>;
|
||||
interrupts = <0 3 0x04 0 12 0x04>;
|
||||
};
|
||||
|
||||
aipstz@0207c000 { /* AIPSTZ1 */
|
||||
reg = <0x0207c000 0x4000>;
|
||||
};
|
||||
|
||||
pwm@02080000 { /* PWM1 */
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 0x04>;
|
||||
};
|
||||
|
||||
pwm@02084000 { /* PWM2 */
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 0x04>;
|
||||
};
|
||||
|
||||
pwm@02088000 { /* PWM3 */
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 0x04>;
|
||||
};
|
||||
|
||||
pwm@0208c000 { /* PWM4 */
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 0x04>;
|
||||
};
|
||||
|
||||
flexcan@02090000 { /* CAN1 */
|
||||
reg = <0x02090000 0x4000>;
|
||||
interrupts = <0 110 0x04>;
|
||||
};
|
||||
|
||||
flexcan@02094000 { /* CAN2 */
|
||||
reg = <0x02094000 0x4000>;
|
||||
interrupts = <0 111 0x04>;
|
||||
};
|
||||
|
||||
gpt@02098000 {
|
||||
compatible = "fsl,imx6q-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 0x04>;
|
||||
};
|
||||
|
||||
gpio0: gpio@0209c000 { /* GPIO1 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x0209c000 0x4000>;
|
||||
interrupts = <0 66 0x04 0 67 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio1: gpio@020a0000 { /* GPIO2 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020a0000 0x4000>;
|
||||
interrupts = <0 68 0x04 0 69 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio2: gpio@020a4000 { /* GPIO3 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020a4000 0x4000>;
|
||||
interrupts = <0 70 0x04 0 71 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio3: gpio@020a8000 { /* GPIO4 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020a8000 0x4000>;
|
||||
interrupts = <0 72 0x04 0 73 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio4: gpio@020ac000 { /* GPIO5 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020ac000 0x4000>;
|
||||
interrupts = <0 74 0x04 0 75 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@020b0000 { /* GPIO6 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020b0000 0x4000>;
|
||||
interrupts = <0 76 0x04 0 77 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio6: gpio@020b4000 { /* GPIO7 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020b4000 0x4000>;
|
||||
interrupts = <0 78 0x04 0 79 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
kpp@020b8000 {
|
||||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 0x04>;
|
||||
};
|
||||
|
||||
wdog@020bc000 { /* WDOG1 */
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@020c0000 { /* WDOG2 */
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
};
|
||||
|
||||
anatop@020c8000 {
|
||||
compatible = "fsl,imx6q-anatop";
|
||||
reg = <0x020c8000 0x1000>;
|
||||
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
|
||||
};
|
||||
|
||||
usbphy@020c9000 { /* USBPHY1 */
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 0x04>;
|
||||
};
|
||||
|
||||
usbphy@020ca000 { /* USBPHY2 */
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 0x04>;
|
||||
};
|
||||
|
||||
snvs@020cc000 {
|
||||
reg = <0x020cc000 0x4000>;
|
||||
interrupts = <0 19 0x04 0 20 0x04>;
|
||||
};
|
||||
|
||||
epit@020d0000 { /* EPIT1 */
|
||||
reg = <0x020d0000 0x4000>;
|
||||
interrupts = <0 56 0x04>;
|
||||
};
|
||||
|
||||
epit@020d4000 { /* EPIT2 */
|
||||
reg = <0x020d4000 0x4000>;
|
||||
interrupts = <0 57 0x04>;
|
||||
};
|
||||
|
||||
src@020d8000 {
|
||||
compatible = "fsl,imx6q-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 0x04 0 96 0x04>;
|
||||
};
|
||||
|
||||
gpc@020dc000 {
|
||||
compatible = "fsl,imx6q-gpc";
|
||||
reg = <0x020dc000 0x4000>;
|
||||
interrupts = <0 89 0x04 0 90 0x04>;
|
||||
};
|
||||
|
||||
iomuxc@020e0000 {
|
||||
reg = <0x020e0000 0x4000>;
|
||||
};
|
||||
|
||||
dcic@020e4000 { /* DCIC1 */
|
||||
reg = <0x020e4000 0x4000>;
|
||||
interrupts = <0 124 0x04>;
|
||||
};
|
||||
|
||||
dcic@020e8000 { /* DCIC2 */
|
||||
reg = <0x020e8000 0x4000>;
|
||||
interrupts = <0 125 0x04>;
|
||||
};
|
||||
|
||||
sdma@020ec000 {
|
||||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 0x04>;
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02100000 0x100000>;
|
||||
ranges;
|
||||
|
||||
caam@02100000 {
|
||||
reg = <0x02100000 0x40000>;
|
||||
interrupts = <0 105 0x04 0 106 0x04>;
|
||||
};
|
||||
|
||||
aipstz@0217c000 { /* AIPSTZ2 */
|
||||
reg = <0x0217c000 0x4000>;
|
||||
};
|
||||
|
||||
enet@02188000 {
|
||||
compatible = "fsl,imx6q-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts = <0 118 0x04 0 119 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mlb@0218c000 {
|
||||
reg = <0x0218c000 0x4000>;
|
||||
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
|
||||
};
|
||||
|
||||
usdhc@02190000 { /* uSDHC1 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc@02194000 { /* uSDHC2 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@021a0000 { /* I2C1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@021a4000 { /* I2C2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@021a8000 { /* I2C3 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
romcp@021ac000 {
|
||||
reg = <0x021ac000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc@021b0000 { /* MMDC0 */
|
||||
compatible = "fsl,imx6q-mmdc";
|
||||
reg = <0x021b0000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc@021b4000 { /* MMDC1 */
|
||||
reg = <0x021b4000 0x4000>;
|
||||
};
|
||||
|
||||
weim@021b8000 {
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <0 14 0x04>;
|
||||
};
|
||||
|
||||
ocotp@021bc000 {
|
||||
reg = <0x021bc000 0x4000>;
|
||||
};
|
||||
|
||||
ocotp@021c0000 {
|
||||
reg = <0x021c0000 0x4000>;
|
||||
interrupts = <0 21 0x04>;
|
||||
};
|
||||
|
||||
tzasc@021d0000 { /* TZASC1 */
|
||||
reg = <0x021d0000 0x4000>;
|
||||
interrupts = <0 108 0x04>;
|
||||
};
|
||||
|
||||
tzasc@021d4000 { /* TZASC2 */
|
||||
reg = <0x021d4000 0x4000>;
|
||||
interrupts = <0 109 0x04>;
|
||||
};
|
||||
|
||||
audmux@021d8000 {
|
||||
reg = <0x021d8000 0x4000>;
|
||||
};
|
||||
|
||||
mipi@021dc000 { /* MIPI-CSI */
|
||||
reg = <0x021dc000 0x4000>;
|
||||
};
|
||||
|
||||
mipi@021e0000 { /* MIPI-DSI */
|
||||
reg = <0x021e0000 0x4000>;
|
||||
};
|
||||
|
||||
vdoa@021e4000 {
|
||||
reg = <0x021e4000 0x4000>;
|
||||
interrupts = <0 18 0x04>;
|
||||
};
|
||||
|
||||
uart1: uart@021e8000 { /* UART2 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@021ec000 { /* UART3 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@021f0000 { /* UART4 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: uart@021f4000 { /* UART5 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
24
arch/arm/boot/dts/msm8660-surf.dts
Normal file
24
arch/arm/boot/dts/msm8660-surf.dts
Normal file
@ -0,0 +1,24 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM8660 SURF";
|
||||
compatible = "qcom,msm8660-surf", "qcom,msm8660";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@02080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = < 0x02080000 0x1000 >,
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
||||
serial@19c400000 {
|
||||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <195>;
|
||||
};
|
||||
};
|
29
arch/arm/boot/dts/omap3-beagle.dts
Normal file
29
arch/arm/boot/dts/omap3-beagle.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 BeagleBoard";
|
||||
compatible = "ti,omap3-beagle", "ti,omap3";
|
||||
|
||||
/*
|
||||
* Since the initial device tree board file does not create any
|
||||
* devices (MMC, network...), the only way to boot is to provide a
|
||||
* ramdisk.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
};
|
63
arch/arm/boot/dts/omap3.dtsi
Normal file
63
arch/arm/boot/dts/omap3.dtsi
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP3 SoC
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap3430", "ti,omap3";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
iva {
|
||||
compatible = "ti,iva2.2";
|
||||
ti,hwmods = "iva";
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
intc: interrupt-controller@1 {
|
||||
compatible = "ti,omap3-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
29
arch/arm/boot/dts/omap4-panda.dts
Normal file
29
arch/arm/boot/dts/omap4-panda.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 PandaBoard";
|
||||
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
|
||||
|
||||
/*
|
||||
* Since the initial device tree board file does not create any
|
||||
* devices (MMC, network...), the only way to boot is to provide a
|
||||
* ramdisk.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
};
|
29
arch/arm/boot/dts/omap4-sdp.dts
Normal file
29
arch/arm/boot/dts/omap4-sdp.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 SDP board";
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
|
||||
|
||||
/*
|
||||
* Since the initial device tree board file does not create any
|
||||
* devices (MMC, network...), the only way to boot is to provide a
|
||||
* ramdisk.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
};
|
103
arch/arm/boot/dts/omap4.dtsi
Normal file
103
arch/arm/boot/dts/omap4.dtsi
Normal file
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Carveout for multimedia usecases
|
||||
* It should be the last 48MB of the first 512MB memory part
|
||||
* In theory, it should not even exist. That zone should be reserved
|
||||
* dynamically during the .reserve callback.
|
||||
*/
|
||||
/memreserve/ 0x9d000000 0x03000000;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap4430", "ti,omap4";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
ti,hwmods = "dsp";
|
||||
};
|
||||
|
||||
iva {
|
||||
compatible = "ti,ivahd";
|
||||
ti,hwmods = "iva";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
*
|
||||
* MPU -+-- MPU_PRIVATE - GIC, L2
|
||||
* |
|
||||
* +----------------+----------+
|
||||
* | | |
|
||||
* + +- EMIF - DDR |
|
||||
* | | |
|
||||
* | + +--------+
|
||||
* | | |
|
||||
* | +- L4_ABE - AESS, MCBSP, TIMERs...
|
||||
* | |
|
||||
* +- L3_MAIN --+- L4_CORE - IPs...
|
||||
* |
|
||||
* +- L4_PER - IPs...
|
||||
* |
|
||||
* +- L4_CFG -+- L4_WKUP - IPs...
|
||||
* | |
|
||||
* | +- IPs...
|
||||
* +- IPU ----+
|
||||
* | |
|
||||
* +- DSP ----+
|
||||
* | |
|
||||
* +- DSS ----+
|
||||
*
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
};
|
||||
};
|
||||
};
|
249
arch/arm/boot/dts/picoxcell-pc3x2.dtsi
Normal file
249
arch/arm/boot/dts/picoxcell-pc3x2.dtsi
Normal file
@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Picochip, Jamie Iles
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
model = "Picochip picoXcell PC3X2";
|
||||
compatible = "picochip,pc3x2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,1176jz-s";
|
||||
clock-frequency = <400000000>;
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pclk: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
clock-outputs = "bus", "pclk";
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
};
|
||||
|
||||
paxi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80000000 0x400000>;
|
||||
|
||||
emac: gem@30000 {
|
||||
compatible = "cadence,gem";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <31>;
|
||||
};
|
||||
|
||||
dmac1: dmac@40000 {
|
||||
compatible = "snps,dw-dmac";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <25>;
|
||||
};
|
||||
|
||||
dmac2: dmac@50000 {
|
||||
compatible = "snps,dw-dmac";
|
||||
reg = <0x50000 0x10000>;
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
vic0: interrupt-controller@60000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
interrupt-controller;
|
||||
reg = <0x60000 0x1000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
vic1: interrupt-controller@64000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
interrupt-controller;
|
||||
reg = <0x64000 0x1000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
fuse: picoxcell-fuse@80000 {
|
||||
compatible = "picoxcell,fuse-pc3x2";
|
||||
reg = <0x80000 0x10000>;
|
||||
};
|
||||
|
||||
ssi: picoxcell-spi@90000 {
|
||||
compatible = "picoxcell,spi";
|
||||
reg = <0x90000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <10>;
|
||||
};
|
||||
|
||||
ipsec: spacc@100000 {
|
||||
compatible = "picochip,spacc-ipsec";
|
||||
reg = <0x100000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <24>;
|
||||
ref-clock = <&pclk>, "ref";
|
||||
};
|
||||
|
||||
srtp: spacc@140000 {
|
||||
compatible = "picochip,spacc-srtp";
|
||||
reg = <0x140000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
l2_engine: spacc@180000 {
|
||||
compatible = "picochip,spacc-l2";
|
||||
reg = <0x180000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <22>;
|
||||
ref-clock = <&pclk>, "ref";
|
||||
};
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x200000 0x80000>;
|
||||
|
||||
rtc0: rtc@00000 {
|
||||
compatible = "picochip,pc3x2-rtc";
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x00000 0xf>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <8>;
|
||||
};
|
||||
|
||||
timer0: timer@10000 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <4>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x10000 0x14>;
|
||||
};
|
||||
|
||||
timer1: timer@10014 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <5>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x10014 0x14>;
|
||||
};
|
||||
|
||||
timer2: timer@10028 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <6>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x10028 0x14>;
|
||||
};
|
||||
|
||||
timer3: timer@1003c {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <7>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x1003c 0x14>;
|
||||
};
|
||||
|
||||
gpio: gpio@20000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
banka: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <8>;
|
||||
|
||||
regoffset-dat = <0x50>;
|
||||
regoffset-set = <0x00>;
|
||||
regoffset-dirout = <0x04>;
|
||||
};
|
||||
|
||||
bankb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <8>;
|
||||
|
||||
regoffset-dat = <0x54>;
|
||||
regoffset-set = <0x0c>;
|
||||
regoffset-dirout = <0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: uart@30000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x30000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <10>;
|
||||
clock-frequency = <3686400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart1: uart@40000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x40000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <9>;
|
||||
clock-frequency = <3686400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
wdog: watchdog@50000 {
|
||||
compatible = "snps,dw-apb-wdg";
|
||||
reg = <0x50000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <11>;
|
||||
bus-clock = <&pclk>, "bus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rwid-axi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
ebi@50000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x08000000
|
||||
1 0 0x48000000 0x08000000
|
||||
2 0 0x50000000 0x08000000
|
||||
3 0 0x58000000 0x08000000>;
|
||||
};
|
||||
|
||||
axi2pico@c0000000 {
|
||||
compatible = "picochip,axi2pico-pc3x2";
|
||||
reg = <0xc0000000 0x10000>;
|
||||
interrupts = <13 14 15 16 17 18 19 20 21>;
|
||||
};
|
||||
};
|
||||
};
|
365
arch/arm/boot/dts/picoxcell-pc3x3.dtsi
Normal file
365
arch/arm/boot/dts/picoxcell-pc3x3.dtsi
Normal file
@ -0,0 +1,365 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Picochip, Jamie Iles
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
model = "Picochip picoXcell PC3X3";
|
||||
compatible = "picochip,pc3x3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,1176jz-s";
|
||||
cpu-clock = <&arm_clk>, "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
clkgate: clkgate@800a0048 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x800a0048 4>;
|
||||
compatible = "picochip,pc3x3-clk-gate";
|
||||
|
||||
tzprot_clk: clock@0 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
spi_clk: clock@1 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <1>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
dmac0_clk: clock@2 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <2>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
dmac1_clk: clock@3 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <3>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
ebi_clk: clock@4 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <4>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
ipsec_clk: clock@5 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <5>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
l2_clk: clock@6 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <6>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
trng_clk: clock@7 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <7>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
fuse_clk: clock@8 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <8>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
|
||||
otp_clk: clock@9 {
|
||||
compatible = "picochip,pc3x3-gated-clk";
|
||||
clock-outputs = "bus";
|
||||
picochip,clk-disable-bit = <9>;
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
};
|
||||
|
||||
arm_clk: clock@11 {
|
||||
compatible = "picochip,pc3x3-pll";
|
||||
reg = <0x800a0050 0x8>;
|
||||
picochip,min-freq = <140000000>;
|
||||
picochip,max-freq = <700000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
clock-outputs = "cpu";
|
||||
};
|
||||
|
||||
pclk: clock@12 {
|
||||
compatible = "fixed-clock";
|
||||
clock-outputs = "bus", "pclk";
|
||||
clock-frequency = <200000000>;
|
||||
ref-clock = <&ref_clk>, "ref";
|
||||
};
|
||||
};
|
||||
|
||||
paxi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80000000 0x400000>;
|
||||
|
||||
emac: gem@30000 {
|
||||
compatible = "cadence,gem";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <31>;
|
||||
};
|
||||
|
||||
dmac1: dmac@40000 {
|
||||
compatible = "snps,dw-dmac";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <25>;
|
||||
};
|
||||
|
||||
dmac2: dmac@50000 {
|
||||
compatible = "snps,dw-dmac";
|
||||
reg = <0x50000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
vic0: interrupt-controller@60000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
interrupt-controller;
|
||||
reg = <0x60000 0x1000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
vic1: interrupt-controller@64000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
interrupt-controller;
|
||||
reg = <0x64000 0x1000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
fuse: picoxcell-fuse@80000 {
|
||||
compatible = "picoxcell,fuse-pc3x3";
|
||||
reg = <0x80000 0x10000>;
|
||||
};
|
||||
|
||||
ssi: picoxcell-spi@90000 {
|
||||
compatible = "picoxcell,spi";
|
||||
reg = <0x90000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <10>;
|
||||
};
|
||||
|
||||
ipsec: spacc@100000 {
|
||||
compatible = "picochip,spacc-ipsec";
|
||||
reg = <0x100000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <24>;
|
||||
ref-clock = <&ipsec_clk>, "ref";
|
||||
};
|
||||
|
||||
srtp: spacc@140000 {
|
||||
compatible = "picochip,spacc-srtp";
|
||||
reg = <0x140000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
l2_engine: spacc@180000 {
|
||||
compatible = "picochip,spacc-l2";
|
||||
reg = <0x180000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <22>;
|
||||
ref-clock = <&l2_clk>, "ref";
|
||||
};
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x200000 0x80000>;
|
||||
|
||||
rtc0: rtc@00000 {
|
||||
compatible = "picochip,pc3x2-rtc";
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x00000 0xf>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <8>;
|
||||
};
|
||||
|
||||
timer0: timer@10000 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <4>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x10000 0x14>;
|
||||
};
|
||||
|
||||
timer1: timer@10014 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <5>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x10014 0x14>;
|
||||
};
|
||||
|
||||
gpio: gpio@20000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
banka: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <8>;
|
||||
|
||||
regoffset-dat = <0x50>;
|
||||
regoffset-set = <0x00>;
|
||||
regoffset-dirout = <0x04>;
|
||||
};
|
||||
|
||||
bankb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <16>;
|
||||
|
||||
regoffset-dat = <0x54>;
|
||||
regoffset-set = <0x0c>;
|
||||
regoffset-dirout = <0x10>;
|
||||
};
|
||||
|
||||
bankd: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <30>;
|
||||
|
||||
regoffset-dat = <0x5c>;
|
||||
regoffset-set = <0x24>;
|
||||
regoffset-dirout = <0x28>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: uart@30000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x30000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <10>;
|
||||
clock-frequency = <3686400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart1: uart@40000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x40000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <9>;
|
||||
clock-frequency = <3686400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
wdog: watchdog@50000 {
|
||||
compatible = "snps,dw-apb-wdg";
|
||||
reg = <0x50000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <11>;
|
||||
bus-clock = <&pclk>, "bus";
|
||||
};
|
||||
|
||||
timer2: timer@60000 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <6>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x60000 0x14>;
|
||||
};
|
||||
|
||||
timer3: timer@60014 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <7>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x60014 0x14>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rwid-axi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
ebi@50000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x08000000
|
||||
1 0 0x48000000 0x08000000
|
||||
2 0 0x50000000 0x08000000
|
||||
3 0 0x58000000 0x08000000>;
|
||||
};
|
||||
|
||||
axi2pico@c0000000 {
|
||||
compatible = "picochip,axi2pico-pc3x3";
|
||||
reg = <0xc0000000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <13 14 15 16 17 18 19 20 21>;
|
||||
};
|
||||
|
||||
otp@ffff8000 {
|
||||
compatible = "picochip,otp-pc3x3";
|
||||
reg = <0xffff8000 0x8000>;
|
||||
};
|
||||
};
|
||||
};
|
86
arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
Normal file
86
arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
Normal file
@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Picochip, Jamie Iles
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "picoxcell-pc3x2.dtsi"
|
||||
/ {
|
||||
model = "Picochip PC7302 (PC3X2)";
|
||||
compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &uart0;
|
||||
};
|
||||
|
||||
clocks {
|
||||
ref_clk: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
clock-outputs = "ref";
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rwid-axi {
|
||||
ebi@50000000 {
|
||||
nand: gpio-nand@2,0 {
|
||||
compatible = "gpio-control-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <2 0x0000 0x1000>;
|
||||
bus-clock = <&pclk>, "bus";
|
||||
gpio-control-nand,io-sync-reg =
|
||||
<0x00000000 0x80220000>;
|
||||
|
||||
gpios = <&banka 1 0 /* rdy */
|
||||
&banka 2 0 /* nce */
|
||||
&banka 3 0 /* ale */
|
||||
&banka 4 0 /* cle */
|
||||
0 /* nwp */>;
|
||||
|
||||
boot@100000 {
|
||||
label = "Boot";
|
||||
reg = <0x100000 0x80000>;
|
||||
};
|
||||
|
||||
redundant-boot@200000 {
|
||||
label = "Redundant Boot";
|
||||
reg = <0x200000 0x80000>;
|
||||
};
|
||||
|
||||
boot-env@300000 {
|
||||
label = "Boot Evironment";
|
||||
reg = <0x300000 0x20000>;
|
||||
};
|
||||
|
||||
redundant-boot-env@320000 {
|
||||
label = "Redundant Boot Environment";
|
||||
reg = <0x300000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@380000 {
|
||||
label = "Kernel";
|
||||
reg = <0x380000 0x800000>;
|
||||
};
|
||||
|
||||
fs@b80000 {
|
||||
label = "File System";
|
||||
reg = <0xb80000 0xf480000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
92
arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
Normal file
92
arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
Normal file
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Picochip, Jamie Iles
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "picoxcell-pc3x3.dtsi"
|
||||
/ {
|
||||
model = "Picochip PC7302 (PC3X3)";
|
||||
compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &uart0;
|
||||
};
|
||||
|
||||
clocks {
|
||||
ref_clk: clock@10 {
|
||||
compatible = "fixed-clock";
|
||||
clock-outputs = "ref";
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
clkgate: clkgate@800a0048 {
|
||||
clock@4 {
|
||||
picochip,clk-no-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rwid-axi {
|
||||
ebi@50000000 {
|
||||
nand: gpio-nand@2,0 {
|
||||
compatible = "gpio-control-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <2 0x0000 0x1000>;
|
||||
bus-clock = <&ebi_clk>, "bus";
|
||||
gpio-control-nand,io-sync-reg =
|
||||
<0x00000000 0x80220000>;
|
||||
|
||||
gpios = <&banka 1 0 /* rdy */
|
||||
&banka 2 0 /* nce */
|
||||
&banka 3 0 /* ale */
|
||||
&banka 4 0 /* cle */
|
||||
0 /* nwp */>;
|
||||
|
||||
boot@100000 {
|
||||
label = "Boot";
|
||||
reg = <0x100000 0x80000>;
|
||||
};
|
||||
|
||||
redundant-boot@200000 {
|
||||
label = "Redundant Boot";
|
||||
reg = <0x200000 0x80000>;
|
||||
};
|
||||
|
||||
boot-env@300000 {
|
||||
label = "Boot Evironment";
|
||||
reg = <0x300000 0x20000>;
|
||||
};
|
||||
|
||||
redundant-boot-env@320000 {
|
||||
label = "Redundant Boot Environment";
|
||||
reg = <0x300000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@380000 {
|
||||
label = "Kernel";
|
||||
reg = <0x380000 0x800000>;
|
||||
};
|
||||
|
||||
fs@b80000 {
|
||||
label = "File System";
|
||||
reg = <0xb80000 0xf480000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@ -39,9 +39,12 @@
|
||||
ranges = <0x40000000 0x40000000 0x80000000>;
|
||||
|
||||
l2-cache-controller@80040000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
|
||||
reg = <0x80040000 0x1000>;
|
||||
interrupts = <59>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,filter-ranges = <0 0x40000000>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@80020000 {
|
||||
@ -67,6 +70,11 @@
|
||||
compatible = "sirf,prima2-rstc";
|
||||
reg = <0x88010000 0x1000>;
|
||||
};
|
||||
|
||||
rsc-controller@88020000 {
|
||||
compatible = "sirf,prima2-rsc";
|
||||
reg = <0x88020000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
mem-iobg {
|
||||
@ -274,7 +282,7 @@
|
||||
gpio: gpio-controller@b0120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,prima2-gpio";
|
||||
compatible = "sirf,prima2-gpio-pinmux";
|
||||
reg = <0xb0120000 0x10000>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
@ -358,7 +366,7 @@
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,prima2-rtciobg", "simple-bus";
|
||||
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80030000 0x10000>;
|
||||
|
@ -66,5 +66,6 @@
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
support-8bit;
|
||||
};
|
||||
};
|
||||
|
@ -25,4 +25,8 @@
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
support-8bit;
|
||||
};
|
||||
};
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user