Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-27 06:31:52 +00:00
Code Issues Packages Projects Releases Wiki Activity

DT IRQ and clock support for Versatile platforms

Browse Source 
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJTqdFdAAoJEMhvYp4jgsXiH0IH/iswt8+Vnk5XV+d5U18sxhcp
 TG9UW3mOnaaNIq3oeyQIXanKbWoSSmiE6FeFO6JqUjHZlutAaah+3EhUfYihZyAC
 +LsFHA1rzhBzKJlwso5/m52Gj+Feuk6FtUsthRqOYaM/uFz43/uAwX9I53TLUHzK
 Ef3uEUMiddmwZwZ+ODQMLnVKp6gKEgBjB4YLVo8HZ//Tm3P6nuHdp3V/u/TTmU8r
 SqGQ1Uyl/6nhRtfJS+6BcWU/V95lN1FoGORh758ZRh41xKfRM7T2q3/aN1Tqa3Bu
 NqQJ1oDwBj18yHZAKDR2VMx0zIV0PE/gyWZufBi8F+5fTt7x+lFf0dlUyJelPbo=
 =JWtP
 -----END PGP SIGNATURE-----

Merge tag 'versatile-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next/soc

Merge "DT IRQ and clock support for Versatile platforms" from Rob Herring.

This branch moves IRQ and clock support over to DT for the versatile
platforms.

* tag 'versatile-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  clk: versatile: add versatile OSC support
  dts: versatile: add clock tree
  ARM: timer-sp: allow getting timer1 clock from DT to fallback to legacy clock
  dt/bindings: add compatible string for versatile osc clock
  dt/bindings: arm-boards: add binding for Versatile core module
  dts: versatile: add pl180 compatible strings
  ARM: versatile: remove init_irq hook for DT boot
  ARM: integrator: convert to use irqchip_init
  irqchip: versatile-fpga: add support for arm,versatile-sic
  irqchip: versatile-fpga: Add IRQCHIP_DECLARE support
  dts: versatile: add missing irq controller properties

Tested-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-07-07 21:47:03 -07:00
commit 12af7011e9
11 changed files with 158 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/arm-boards
View File

@ -86,3 +86,9 @@ Interrupt controllers:
compatible = "arm,versatile-sic";
interrupt-controller;
#interrupt-cells = <1>;
Required nodes:
- core-module: the root node to the Versatile platforms must have
a core-module with regs and the compatible strings
"arm,core-module-versatile", "syscon"

4
Documentation/devicetree/bindings/clock/arm-integrator.txt
View File

@ -1,4 +1,4 @@
Clock bindings for ARM Integrator Core Module clocks
Clock bindings for ARM Integrator and Versatile Core Module clocks
Auxilary Oscillator Clock
@ -12,7 +12,7 @@ parent node.
Required properties:
- compatible: must be "arm,integrator-cm-auxosc"
- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
- #clock-cells: must be <0>
Optional properties:

81
arch/arm/boot/dts/versatile-ab.dts
View File

@ -19,6 +19,41 @@
reg = <0x0 0x08000000>;
};
xtal24mhz: xtal24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
core-module@10000000 {
compatible = "arm,core-module-versatile", "syscon";
reg = <0x10000000 0x200>;
/* OSC1 on AB, OSC4 on PB */
osc1: cm_aux_osc@24M {
#clock-cells = <0>;
compatible = "arm,versatile-cm-auxosc";
clocks = <&xtal24mhz>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
timclk: timclk@1M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
pclk: pclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
};
flash@34000000 {
compatible = "arm,versatile-flash";
reg = <0x34000000 0x4000000>;
@ -59,6 +94,8 @@
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x1000>;
clear-mask = <0xffffffff>;
valid-mask = <0xffffffff>;
};
sic: intc@10003000 {
@ -68,69 +105,93 @@
reg = <0x10003000 0x1000>;
interrupt-parent = <&vic>;
interrupts = <31>; /* Cascaded to vic */
clear-mask = <0xffffffff>;
valid-mask = <0xffc203f8>;
};
dma@10130000 {
compatible = "arm,pl081", "arm,primecell";
reg = <0x10130000 0x1000>;
interrupts = <17>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
uart0: uart@101f1000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f1000 0x1000>;
interrupts = <12>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@101f2000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f2000 0x1000>;
interrupts = <13>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
uart2: uart@101f3000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f3000 0x1000>;
interrupts = <14>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
smc@10100000 {
compatible = "arm,primecell";
reg = <0x10100000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
mpmc@10110000 {
compatible = "arm,primecell";
reg = <0x10110000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
display@10120000 {
compatible = "arm,pl110", "arm,primecell";
reg = <0x10120000 0x1000>;
interrupts = <16>;
clocks = <&osc1>, <&pclk>;
clock-names = "clcd", "apb_pclk";
};
sctl@101e0000 {
compatible = "arm,primecell";
reg = <0x101e0000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
watchdog@101e1000 {
compatible = "arm,primecell";
reg = <0x101e1000 0x1000>;
interrupts = <0>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
timer@101e2000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x101e2000 0x1000>;
interrupts = <4>;
clocks = <&timclk>, <&timclk>, <&pclk>;
clock-names = "timer0", "timer1", "apb_pclk";
};
timer@101e3000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x101e3000 0x1000>;
interrupts = <5>;
clocks = <&timclk>, <&timclk>, <&pclk>;
clock-names = "timer0", "timer1", "apb_pclk";
};
gpio0: gpio@101e4000 {
@ -141,6 +202,8 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
gpio1: gpio@101e5000 {
@ -151,24 +214,32 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
rtc@101e8000 {
compatible = "arm,pl030", "arm,primecell";
reg = <0x101e8000 0x1000>;
interrupts = <10>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
sci@101f0000 {
compatible = "arm,primecell";
reg = <0x101f0000 0x1000>;
interrupts = <15>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
ssp@101f4000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x101f4000 0x1000>;
interrupts = <11>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "SSPCLK", "apb_pclk";
};
fpga {
@ -181,23 +252,31 @@
compatible = "arm,primecell";
reg = <0x4000 0x1000>;
interrupts = <24>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
mmc@5000 {
compatible = "arm,primecell";
compatible = "arm,pl180", "arm,primecell";
reg = < 0x5000 0x1000>;
interrupts-extended = <&vic 22 &sic 2>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "mclk", "apb_pclk";
};
kmi@6000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x6000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <3>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@7000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x7000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <4>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
};
};

12
arch/arm/boot/dts/versatile-pb.dts
View File

@ -13,6 +13,8 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
gpio3: gpio@101e7000 {
@ -23,6 +25,8 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
fpga {
@ -31,17 +35,23 @@
reg = <0x9000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <6>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
sci@a000 {
compatible = "arm,primecell";
reg = <0xa000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <5>;
clocks = <&xtal24mhz>;
clock-names = "apb_pclk";
};
mmc@b000 {
compatible = "arm,primecell";
compatible = "arm,pl180", "arm,primecell";
reg = <0xb000 0x1000>;
interrupts-extended = <&vic 23 &sic 2>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "mclk", "apb_pclk";
};
};
};

4
arch/arm/common/timer-sp.c
View File

@ -233,13 +233,13 @@ static void __init sp804_of_init(struct device_node *np)
if (IS_ERR(clk1))
clk1 = NULL;
/* Get the 2nd clock if the timer has 2 timer clocks */
/* Get the 2nd clock if the timer has 3 timer clocks */
if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
clk2 = of_clk_get(np, 1);
if (IS_ERR(clk2)) {
pr_err("sp804: %s clock not found: %d\n", np->name,
(int)PTR_ERR(clk2));
goto err;
clk2 = NULL;
}
} else
clk2 = clk1;

10
arch/arm/mach-integrator/integrator_ap.c
View File

@ -31,7 +31,7 @@
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/irqchip.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>
#include <linux/platform_data/clk-integrator.h>
@ -439,15 +439,10 @@ static void __init ap_of_timer_init(void)
integrator_clockevent_init(rate, base, irq);
}
static const struct of_device_id fpga_irq_of_match[] __initconst = {
{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
{ /* Sentinel */ }
};
static void __init ap_init_irq_of(void)
{
cm_init();
of_irq_init(fpga_irq_of_match);
irqchip_init();
}
/* For the Device Tree, add in the UART callbacks as AUXDATA */
@ -558,7 +553,6 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
.map_io = ap_map_io,
.init_early = ap_init_early,
.init_irq = ap_init_irq_of,
.handle_irq = fpga_handle_irq,
.init_time = ap_of_timer_init,
.init_machine = ap_init_of,
.restart = integrator_restart,

10
arch/arm/mach-integrator/integrator_cp.c
View File

@ -20,7 +20,7 @@
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/irqchip.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/of_irq.h>
@ -235,15 +235,10 @@ static void __init intcp_init_early(void)
sched_clock_register(intcp_read_sched_clock, 32, 24000000);
}
static const struct of_device_id fpga_irq_of_match[] __initconst = {
{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
{ /* Sentinel */ }
};
static void __init intcp_init_irq_of(void)
{
cm_init();
of_irq_init(fpga_irq_of_match);
irqchip_init();
}
/*
@ -329,7 +324,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
.map_io = intcp_map_io,
.init_early = intcp_init_early,
.init_irq = intcp_init_irq_of,
.handle_irq = fpga_handle_irq,
.init_machine = intcp_init_of,
.restart = integrator_restart,
.dt_compat = intcp_dt_board_compat,

1
arch/arm/mach-versatile/versatile_dt.c
View File

@ -44,7 +44,6 @@ static const char *versatile_dt_match[] __initconst = {
DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
.map_io = versatile_map_io,
.init_early = versatile_init_early,
.init_irq = versatile_init_irq,
.init_machine = versatile_dt_init,
.dt_compat = versatile_dt_match,
.restart = versatile_restart,

3
drivers/clk/versatile/Makefile
View File

@ -1,6 +1,5 @@
# Makefile for Versatile-specific clocks
obj-$(CONFIG_ICST) += clk-icst.o
obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o
obj-$(CONFIG_ICST) += clk-icst.o clk-versatile.o
obj-$(CONFIG_INTEGRATOR_IMPD1) += clk-impd1.o
obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o
obj-$(CONFIG_ARCH_VEXPRESS) += clk-vexpress.o

38
drivers/clk/versatile/clk-integrator.c → drivers/clk/versatile/clk-versatile.c
View File

@ -1,5 +1,6 @@
/*
* Clock driver for the ARM Integrator/AP and Integrator/CP boards
* Clock driver for the ARM Integrator/AP, Integrator/CP, Versatile AB and
* Versatile PB boards.
* Copyright (C) 2012 Linus Walleij
*
* This program is free software; you can redistribute it and/or modify
@ -17,6 +18,9 @@
#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
#define VERSATILE_SYS_OSCCLCD_OFFSET 0x1c
#define VERSATILE_SYS_LOCK_OFFSET 0x20
/* Base offset for the core module */
static void __iomem *cm_base;
@ -37,11 +41,27 @@ static const struct clk_icst_desc __initdata cm_auxosc_desc = {
.lock_offset = INTEGRATOR_HDR_LOCK_OFFSET,
};
static void __init of_integrator_cm_osc_setup(struct device_node *np)
static const struct icst_params versatile_auxosc_params = {
.vco_max = ICST307_VCO_MAX,
.vco_min = ICST307_VCO_MIN,
.vd_min = 4 + 8,
.vd_max = 511 + 8,
.rd_min = 1 + 2,
.rd_max = 127 + 2,
.s2div = icst307_s2div,
.idx2s = icst307_idx2s,
};
static const struct clk_icst_desc versatile_auxosc_desc __initconst = {
.params = &versatile_auxosc_params,
.vco_offset = VERSATILE_SYS_OSCCLCD_OFFSET,
.lock_offset = VERSATILE_SYS_LOCK_OFFSET,
};
static void __init cm_osc_setup(struct device_node *np,
const struct clk_icst_desc *desc)
{
struct clk *clk = ERR_PTR(-EINVAL);
const char *clk_name = np->name;
const struct clk_icst_desc *desc = &cm_auxosc_desc;
const char *parent_name;
if (!cm_base) {
@ -65,5 +85,17 @@ static void __init of_integrator_cm_osc_setup(struct device_node *np)
if (!IS_ERR(clk))
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
static void __init of_integrator_cm_osc_setup(struct device_node *np)
{
cm_osc_setup(np, &cm_auxosc_desc);
}
CLK_OF_DECLARE(integrator_cm_auxosc_clk,
"arm,integrator-cm-auxosc", of_integrator_cm_osc_setup);
static void __init of_versatile_cm_osc_setup(struct device_node *np)
{
cm_osc_setup(np, &versatile_auxosc_desc);
}
CLK_OF_DECLARE(versatile_cm_auxosc_clk,
"arm,versatile-cm-auxosc", of_versatile_cm_osc_setup);

18
drivers/irqchip/irq-versatile-fpga.c
View File

@ -14,6 +14,8 @@
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
#define IRQ_STATUS 0x00
#define IRQ_RAW_STATUS 0x04
#define IRQ_ENABLE_SET 0x08
@ -26,6 +28,8 @@
#define FIQ_ENABLE_SET 0x28
#define FIQ_ENABLE_CLEAR 0x2C
#define PIC_ENABLES 0x20 /* set interrupt pass through bits */
/**
* struct fpga_irq_data - irq data container for the FPGA IRQ controller
* @base: memory offset in virtual memory
@ -201,14 +205,26 @@ int __init fpga_irq_of_init(struct device_node *node,
/* Some chips are cascaded from a parent IRQ */
parent_irq = irq_of_parse_and_map(node, 0);
if (!parent_irq)
if (!parent_irq) {
set_handle_irq(fpga_handle_irq);
parent_irq = -1;
}
fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
writel(clear_mask, base + IRQ_ENABLE_CLEAR);
writel(clear_mask, base + FIQ_ENABLE_CLEAR);
/*
* On Versatile AB/PB, some secondary interrupts have a direct
* pass-thru to the primary controller for IRQs 20 and 22-31 which need
* to be enabled. See section 3.10 of the Versatile AB user guide.
*/
if (of_device_is_compatible(node, "arm,versatile-sic"))
writel(0xffd00000, base + PIC_ENABLES);
return 0;
}
IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
#endif