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PCI/MSI: Reorder functions in msi.c
There is no way to navigate msi.c without banging the head against the wall every now and then because MSI and MSI-X specific functions are intermingled and the code flow is completely non-obvious. Reorder everthing so common helpers, MSI and MSI-X specific functions are grouped together. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20221111122015.459089736@linutronix.de
This commit is contained in:
Ahmed S. Darwish
Thomas Gleixner
parent
88614075a9
commit
12910ffd18
@ -16,6 +16,97 @@
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int pci_msi_enable = 1;
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int pci_msi_ignore_mask;
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/**
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* pci_msi_supported - check whether MSI may be enabled on a device
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* @dev: pointer to the pci_dev data structure of MSI device function
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* @nvec: how many MSIs have been requested?
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*
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* Look at global flags, the device itself, and its parent buses
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* to determine if MSI/-X are supported for the device. If MSI/-X is
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* supported return 1, else return 0.
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**/
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static int pci_msi_supported(struct pci_dev *dev, int nvec)
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{
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struct pci_bus *bus;
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/* MSI must be globally enabled and supported by the device */
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if (!pci_msi_enable)
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return 0;
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if (!dev || dev->no_msi)
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return 0;
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/*
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* You can't ask to have 0 or less MSIs configured.
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* a) it's stupid ..
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* b) the list manipulation code assumes nvec >= 1.
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*/
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if (nvec < 1)
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return 0;
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/*
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* Any bridge which does NOT route MSI transactions from its
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* secondary bus to its primary bus must set NO_MSI flag on
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* the secondary pci_bus.
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*
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* The NO_MSI flag can either be set directly by:
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* - arch-specific PCI host bus controller drivers (deprecated)
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* - quirks for specific PCI bridges
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*
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* or indirectly by platform-specific PCI host bridge drivers by
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* advertising the 'msi_domain' property, which results in
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* the NO_MSI flag when no MSI domain is found for this bridge
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* at probe time.
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*/
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for (bus = dev->bus; bus; bus = bus->parent)
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if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
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return 0;
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return 1;
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}
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static void pcim_msi_release(void *pcidev)
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{
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struct pci_dev *dev = pcidev;
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dev->is_msi_managed = false;
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pci_free_irq_vectors(dev);
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}
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/*
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* Needs to be separate from pcim_release to prevent an ordering problem
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* vs. msi_device_data_release() in the MSI core code.
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*/
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static int pcim_setup_msi_release(struct pci_dev *dev)
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{
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int ret;
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if (!pci_is_managed(dev) || dev->is_msi_managed)
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return 0;
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ret = devm_add_action(&dev->dev, pcim_msi_release, dev);
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if (!ret)
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dev->is_msi_managed = true;
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return ret;
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}
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/*
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* Ordering vs. devres: msi device data has to be installed first so that
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* pcim_msi_release() is invoked before it on device release.
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*/
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static int pci_setup_msi_context(struct pci_dev *dev)
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{
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int ret = msi_setup_device_data(&dev->dev);
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if (!ret)
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ret = pcim_setup_msi_release(dev);
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return ret;
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}
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/*
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* Helper functions for mask/unmask and MSI message handling
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*/
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void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set)
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{
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raw_spinlock_t *lock = &to_pci_dev(desc->dev)->msi_lock;
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@ -163,15 +254,8 @@ void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
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}
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EXPORT_SYMBOL_GPL(pci_write_msi_msg);
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void pci_free_msi_irqs(struct pci_dev *dev)
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{
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pci_msi_teardown_msi_irqs(dev);
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if (dev->msix_base) {
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iounmap(dev->msix_base);
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dev->msix_base = NULL;
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}
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}
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/* PCI/MSI specific functionality */
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static void pci_intx_for_msi(struct pci_dev *dev, int enable)
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{
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@ -190,111 +274,6 @@ static void pci_msi_set_enable(struct pci_dev *dev, int enable)
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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/*
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* Architecture override returns true when the PCI MSI message should be
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* written by the generic restore function.
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*/
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bool __weak arch_restore_msi_irqs(struct pci_dev *dev)
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{
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return true;
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}
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void __pci_restore_msi_state(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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u16 control;
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if (!dev->msi_enabled)
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return;
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entry = irq_get_msi_desc(dev->irq);
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pci_intx_for_msi(dev, 0);
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pci_msi_set_enable(dev, 0);
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if (arch_restore_msi_irqs(dev))
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__pci_write_msi_msg(entry, &entry->msg);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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pci_msi_update_mask(entry, 0, 0);
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
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{
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u16 ctrl;
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
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ctrl &= ~clear;
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ctrl |= set;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
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}
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void __pci_restore_msix_state(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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bool write_msg;
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if (!dev->msix_enabled)
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return;
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/* route the table */
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pci_intx_for_msi(dev, 0);
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pci_msix_clear_and_set_ctrl(dev, 0,
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PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
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write_msg = arch_restore_msi_irqs(dev);
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msi_lock_descs(&dev->dev);
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msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
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if (write_msg)
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__pci_write_msi_msg(entry, &entry->msg);
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pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
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}
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msi_unlock_descs(&dev->dev);
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pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
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}
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static void pcim_msi_release(void *pcidev)
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{
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struct pci_dev *dev = pcidev;
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dev->is_msi_managed = false;
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pci_free_irq_vectors(dev);
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}
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/*
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* Needs to be separate from pcim_release to prevent an ordering problem
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* vs. msi_device_data_release() in the MSI core code.
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*/
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static int pcim_setup_msi_release(struct pci_dev *dev)
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{
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int ret;
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if (!pci_is_managed(dev) || dev->is_msi_managed)
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return 0;
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ret = devm_add_action(&dev->dev, pcim_msi_release, dev);
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if (!ret)
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dev->is_msi_managed = true;
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return ret;
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}
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/*
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* Ordering vs. devres: msi device data has to be installed first so that
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* pcim_msi_release() is invoked before it on device release.
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*/
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static int pci_setup_msi_context(struct pci_dev *dev)
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{
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int ret = msi_setup_device_data(&dev->dev);
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if (!ret)
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ret = pcim_setup_msi_release(dev);
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return ret;
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}
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static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
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struct irq_affinity_desc *masks)
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{
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@ -415,6 +394,149 @@ unlock:
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return ret;
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}
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int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
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struct irq_affinity *affd)
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{
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int nvec;
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int rc;
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if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
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return -EINVAL;
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/* Check whether driver already requested MSI-X IRQs */
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if (dev->msix_enabled) {
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pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
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return -EINVAL;
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}
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if (maxvec < minvec)
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return -ERANGE;
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if (WARN_ON_ONCE(dev->msi_enabled))
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return -EINVAL;
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nvec = pci_msi_vec_count(dev);
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if (nvec < 0)
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return nvec;
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if (nvec < minvec)
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return -ENOSPC;
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if (nvec > maxvec)
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nvec = maxvec;
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rc = pci_setup_msi_context(dev);
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if (rc)
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return rc;
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for (;;) {
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if (affd) {
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nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
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if (nvec < minvec)
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return -ENOSPC;
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}
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rc = msi_capability_init(dev, nvec, affd);
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if (rc == 0)
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return nvec;
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if (rc < 0)
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return rc;
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if (rc < minvec)
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return -ENOSPC;
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nvec = rc;
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}
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}
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/**
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* pci_msi_vec_count - Return the number of MSI vectors a device can send
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* @dev: device to report about
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*
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* This function returns the number of MSI vectors a device requested via
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* Multiple Message Capable register. It returns a negative errno if the
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* device is not capable sending MSI interrupts. Otherwise, the call succeeds
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* and returns a power of two, up to a maximum of 2^5 (32), according to the
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* MSI specification.
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**/
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int pci_msi_vec_count(struct pci_dev *dev)
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{
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int ret;
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u16 msgctl;
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if (!dev->msi_cap)
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return -EINVAL;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
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ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
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return ret;
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}
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EXPORT_SYMBOL(pci_msi_vec_count);
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/*
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* Architecture override returns true when the PCI MSI message should be
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* written by the generic restore function.
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*/
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bool __weak arch_restore_msi_irqs(struct pci_dev *dev)
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{
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return true;
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}
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void __pci_restore_msi_state(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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u16 control;
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if (!dev->msi_enabled)
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return;
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entry = irq_get_msi_desc(dev->irq);
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pci_intx_for_msi(dev, 0);
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pci_msi_set_enable(dev, 0);
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if (arch_restore_msi_irqs(dev))
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__pci_write_msi_msg(entry, &entry->msg);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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pci_msi_update_mask(entry, 0, 0);
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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void pci_msi_shutdown(struct pci_dev *dev)
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{
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struct msi_desc *desc;
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if (!pci_msi_enable || !dev || !dev->msi_enabled)
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return;
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pci_msi_set_enable(dev, 0);
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pci_intx_for_msi(dev, 1);
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dev->msi_enabled = 0;
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/* Return the device with MSI unmasked as initial states */
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desc = msi_first_desc(&dev->dev, MSI_DESC_ALL);
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if (!WARN_ON_ONCE(!desc))
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pci_msi_unmask(desc, msi_multi_mask(desc));
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/* Restore dev->irq to its default pin-assertion IRQ */
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dev->irq = desc->pci.msi_attrib.default_irq;
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pcibios_alloc_irq(dev);
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}
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/* PCI/MSI-X specific functionality */
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static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
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{
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u16 ctrl;
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
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ctrl &= ~clear;
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ctrl |= set;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
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}
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static void __iomem *msix_map_region(struct pci_dev *dev,
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unsigned int nr_entries)
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{
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@ -599,101 +721,6 @@ out_disable:
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return ret;
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}
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/**
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* pci_msi_supported - check whether MSI may be enabled on a device
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* @dev: pointer to the pci_dev data structure of MSI device function
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* @nvec: how many MSIs have been requested?
|
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*
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* Look at global flags, the device itself, and its parent buses
|
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* to determine if MSI/-X are supported for the device. If MSI/-X is
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* supported return 1, else return 0.
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**/
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static int pci_msi_supported(struct pci_dev *dev, int nvec)
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{
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struct pci_bus *bus;
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/* MSI must be globally enabled and supported by the device */
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if (!pci_msi_enable)
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return 0;
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if (!dev || dev->no_msi)
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return 0;
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/*
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* You can't ask to have 0 or less MSIs configured.
|
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* a) it's stupid ..
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* b) the list manipulation code assumes nvec >= 1.
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*/
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if (nvec < 1)
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return 0;
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/*
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* Any bridge which does NOT route MSI transactions from its
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* secondary bus to its primary bus must set NO_MSI flag on
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* the secondary pci_bus.
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*
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* The NO_MSI flag can either be set directly by:
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* - arch-specific PCI host bus controller drivers (deprecated)
|
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* - quirks for specific PCI bridges
|
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*
|
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* or indirectly by platform-specific PCI host bridge drivers by
|
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* advertising the 'msi_domain' property, which results in
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* the NO_MSI flag when no MSI domain is found for this bridge
|
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* at probe time.
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*/
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for (bus = dev->bus; bus; bus = bus->parent)
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if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
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return 0;
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return 1;
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}
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/**
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* pci_msi_vec_count - Return the number of MSI vectors a device can send
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* @dev: device to report about
|
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*
|
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* This function returns the number of MSI vectors a device requested via
|
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* Multiple Message Capable register. It returns a negative errno if the
|
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* device is not capable sending MSI interrupts. Otherwise, the call succeeds
|
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* and returns a power of two, up to a maximum of 2^5 (32), according to the
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* MSI specification.
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**/
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int pci_msi_vec_count(struct pci_dev *dev)
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{
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int ret;
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u16 msgctl;
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if (!dev->msi_cap)
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return -EINVAL;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
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ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
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return ret;
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}
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EXPORT_SYMBOL(pci_msi_vec_count);
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void pci_msi_shutdown(struct pci_dev *dev)
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{
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struct msi_desc *desc;
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if (!pci_msi_enable || !dev || !dev->msi_enabled)
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return;
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pci_msi_set_enable(dev, 0);
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pci_intx_for_msi(dev, 1);
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dev->msi_enabled = 0;
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/* Return the device with MSI unmasked as initial states */
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desc = msi_first_desc(&dev->dev, MSI_DESC_ALL);
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if (!WARN_ON_ONCE(!desc))
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pci_msi_unmask(desc, msi_multi_mask(desc));
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|
||||
/* Restore dev->irq to its default pin-assertion IRQ */
|
||||
dev->irq = desc->pci.msi_attrib.default_irq;
|
||||
pcibios_alloc_irq(dev);
|
||||
}
|
||||
|
||||
static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
|
||||
int nvec, struct irq_affinity *affd, int flags)
|
||||
{
|
||||
@ -729,82 +756,6 @@ static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
|
||||
return msix_capability_init(dev, entries, nvec, affd);
|
||||
}
|
||||
|
||||
void pci_msix_shutdown(struct pci_dev *dev)
|
||||
{
|
||||
struct msi_desc *desc;
|
||||
|
||||
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
||||
return;
|
||||
|
||||
if (pci_dev_is_disconnected(dev)) {
|
||||
dev->msix_enabled = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Return the device with MSI-X masked as initial states */
|
||||
msi_for_each_desc(desc, &dev->dev, MSI_DESC_ALL)
|
||||
pci_msix_mask(desc);
|
||||
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
pci_intx_for_msi(dev, 1);
|
||||
dev->msix_enabled = 0;
|
||||
pcibios_alloc_irq(dev);
|
||||
}
|
||||
|
||||
int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
|
||||
struct irq_affinity *affd)
|
||||
{
|
||||
int nvec;
|
||||
int rc;
|
||||
|
||||
if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
|
||||
return -EINVAL;
|
||||
|
||||
/* Check whether driver already requested MSI-X IRQs */
|
||||
if (dev->msix_enabled) {
|
||||
pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (maxvec < minvec)
|
||||
return -ERANGE;
|
||||
|
||||
if (WARN_ON_ONCE(dev->msi_enabled))
|
||||
return -EINVAL;
|
||||
|
||||
nvec = pci_msi_vec_count(dev);
|
||||
if (nvec < 0)
|
||||
return nvec;
|
||||
if (nvec < minvec)
|
||||
return -ENOSPC;
|
||||
|
||||
if (nvec > maxvec)
|
||||
nvec = maxvec;
|
||||
|
||||
rc = pci_setup_msi_context(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
for (;;) {
|
||||
if (affd) {
|
||||
nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
|
||||
if (nvec < minvec)
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
rc = msi_capability_init(dev, nvec, affd);
|
||||
if (rc == 0)
|
||||
return nvec;
|
||||
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
if (rc < minvec)
|
||||
return -ENOSPC;
|
||||
|
||||
nvec = rc;
|
||||
}
|
||||
}
|
||||
|
||||
int __pci_enable_msix_range(struct pci_dev *dev,
|
||||
struct msix_entry *entries, int minvec,
|
||||
int maxvec, struct irq_affinity *affd,
|
||||
@ -847,6 +798,68 @@ int __pci_enable_msix_range(struct pci_dev *dev,
|
||||
}
|
||||
}
|
||||
|
||||
void __pci_restore_msix_state(struct pci_dev *dev)
|
||||
{
|
||||
struct msi_desc *entry;
|
||||
bool write_msg;
|
||||
|
||||
if (!dev->msix_enabled)
|
||||
return;
|
||||
|
||||
/* route the table */
|
||||
pci_intx_for_msi(dev, 0);
|
||||
pci_msix_clear_and_set_ctrl(dev, 0,
|
||||
PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
|
||||
|
||||
write_msg = arch_restore_msi_irqs(dev);
|
||||
|
||||
msi_lock_descs(&dev->dev);
|
||||
msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
|
||||
if (write_msg)
|
||||
__pci_write_msi_msg(entry, &entry->msg);
|
||||
pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
|
||||
}
|
||||
msi_unlock_descs(&dev->dev);
|
||||
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
}
|
||||
|
||||
void pci_msix_shutdown(struct pci_dev *dev)
|
||||
{
|
||||
struct msi_desc *desc;
|
||||
|
||||
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
||||
return;
|
||||
|
||||
if (pci_dev_is_disconnected(dev)) {
|
||||
dev->msix_enabled = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Return the device with MSI-X masked as initial states */
|
||||
msi_for_each_desc(desc, &dev->dev, MSI_DESC_ALL)
|
||||
pci_msix_mask(desc);
|
||||
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
pci_intx_for_msi(dev, 1);
|
||||
dev->msix_enabled = 0;
|
||||
pcibios_alloc_irq(dev);
|
||||
}
|
||||
|
||||
/* Common interfaces */
|
||||
|
||||
void pci_free_msi_irqs(struct pci_dev *dev)
|
||||
{
|
||||
pci_msi_teardown_msi_irqs(dev);
|
||||
|
||||
if (dev->msix_base) {
|
||||
iounmap(dev->msix_base);
|
||||
dev->msix_base = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Misc. infrastructure */
|
||||
|
||||
struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
|
||||
{
|
||||
return to_pci_dev(desc->dev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user