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clk: mediatek: mt8183: Move apmixedsys clock driver to its own file
In preparation for migrating all other mt8183 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it and fix some indentation issues in the PLLs table. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-20-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
parent
beb47f1942
commit
127fadf7a4
@ -74,7 +74,7 @@ obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
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obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
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obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
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obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
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obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183-apmixedsys.o clk-mt8183.o
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obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
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obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
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obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o
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193
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
Normal file
193
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
Normal file
@ -0,0 +1,193 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Weiyi Lu <weiyi.lu@mediatek.com>
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* Copyright (c) 2023 Collabora, Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "clk-pll.h"
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static const struct mtk_gate_regs apmixed_cg_regs = {
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.set_ofs = 0x20,
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.clr_ofs = 0x20,
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.sta_ofs = 0x20,
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};
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#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
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GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
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_shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
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#define GATE_APMIXED(_id, _name, _parent, _shift) \
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GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
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/*
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* CRITICAL CLOCK:
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* apmixed_appll26m is the toppest clock gate of all PLLs.
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*/
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static const struct mtk_gate apmixed_clks[] = {
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/* AUDIO0 */
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GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", "f_f26m_ck", 4),
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GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
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"f_f26m_ck", 5, CLK_IS_CRITICAL),
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GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck", 6),
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GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", "f_f26m_ck", 7),
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GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", "f_f26m_ck", 8),
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GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", "f_f26m_ck", 9),
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GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck", 11),
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GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", "f_f26m_ck", 13),
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GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", "f_f26m_ck", 14),
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GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck", 16),
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GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", "f_f26m_ck", 17),
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};
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#define MT8183_PLL_FMAX (3800UL * MHZ)
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#define MT8183_PLL_FMIN (1500UL * MHZ)
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg, _div_table) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8183_PLL_FMAX, \
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.fmin = MT8183_PLL_FMIN, \
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.pcwbits = _pcwbits, \
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.pcwibits = _pcwibits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.div_table = _div_table, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg) \
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PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg, NULL)
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static const struct mtk_pll_div_table armpll_div_table[] = {
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{ .div = 0, .freq = MT8183_PLL_FMAX },
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{ .div = 1, .freq = 1500 * MHZ },
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{ .div = 2, .freq = 750 * MHZ },
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{ .div = 3, .freq = 375 * MHZ },
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{ .div = 4, .freq = 187500000 },
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{ /* sentinel */ }
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};
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static const struct mtk_pll_div_table mfgpll_div_table[] = {
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{ .div = 0, .freq = MT8183_PLL_FMAX },
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{ .div = 1, .freq = 1600 * MHZ },
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{ .div = 2, .freq = 800 * MHZ },
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{ .div = 3, .freq = 400 * MHZ },
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{ .div = 4, .freq = 200 * MHZ },
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{ /* sentinel */ }
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};
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static const struct mtk_pll_data plls[] = {
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PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
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HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
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0x0204, 0, 0, armpll_div_table),
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PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
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HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
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0x0214, 0, 0, armpll_div_table),
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PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
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HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
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0x0294, 0, 0),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
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HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
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0x0224, 0, 0),
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PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
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HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
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0x0234, 0, 0),
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PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0,
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0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
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mfgpll_div_table),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
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0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
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0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
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HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
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0x0274, 0, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
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0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
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0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
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};
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static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (ret)
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return ret;
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ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
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ARRAY_SIZE(apmixed_clks), clk_data);
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if (ret)
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goto unregister_plls;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_gates;
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return 0;
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unregister_gates:
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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return ret;
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}
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static const struct of_device_id of_match_clk_mt8183_apmixed[] = {
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{ .compatible = "mediatek,mt8183-apmixedsys" },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt8183_apmixed_drv = {
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.probe = clk_mt8183_apmixed_probe,
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.driver = {
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.name = "clk-mt8183-apmixed",
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.of_match_table = of_match_clk_mt8183_apmixed,
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},
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};
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builtin_platform_driver(clk_mt8183_apmixed_drv)
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@ -14,7 +14,6 @@
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "clk-mux.h"
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#include "clk-pll.h"
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#include <dt-bindings/clock/mt8183-clk.h>
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@ -941,140 +940,6 @@ static const struct mtk_gate peri_clks[] = {
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GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
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};
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static const struct mtk_gate_regs apmixed_cg_regs = {
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.set_ofs = 0x20,
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.clr_ofs = 0x20,
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.sta_ofs = 0x20,
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};
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#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
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GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
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_shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
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#define GATE_APMIXED(_id, _name, _parent, _shift) \
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GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
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/*
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* CRITICAL CLOCK:
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* apmixed_appll26m is the toppest clock gate of all PLLs.
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*/
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static const struct mtk_gate apmixed_clks[] = {
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/* AUDIO0 */
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GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
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"f_f26m_ck", 4),
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GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
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"f_f26m_ck", 5, CLK_IS_CRITICAL),
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GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
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"f_f26m_ck", 6),
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GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
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"f_f26m_ck", 7),
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GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
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"f_f26m_ck", 8),
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GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
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"f_f26m_ck", 9),
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GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
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"f_f26m_ck", 11),
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GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
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"f_f26m_ck", 13),
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GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
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"f_f26m_ck", 14),
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GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
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"f_f26m_ck", 16),
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GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
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"f_f26m_ck", 17),
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};
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#define MT8183_PLL_FMAX (3800UL * MHZ)
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#define MT8183_PLL_FMIN (1500UL * MHZ)
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg, _div_table) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8183_PLL_FMAX, \
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.fmin = MT8183_PLL_FMIN, \
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.pcwbits = _pcwbits, \
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.pcwibits = _pcwibits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.div_table = _div_table, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg) \
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PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg, NULL)
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static const struct mtk_pll_div_table armpll_div_table[] = {
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{ .div = 0, .freq = MT8183_PLL_FMAX },
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{ .div = 1, .freq = 1500 * MHZ },
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{ .div = 2, .freq = 750 * MHZ },
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{ .div = 3, .freq = 375 * MHZ },
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{ .div = 4, .freq = 187500000 },
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{ } /* sentinel */
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};
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static const struct mtk_pll_div_table mfgpll_div_table[] = {
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{ .div = 0, .freq = MT8183_PLL_FMAX },
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{ .div = 1, .freq = 1600 * MHZ },
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{ .div = 2, .freq = 800 * MHZ },
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{ .div = 3, .freq = 400 * MHZ },
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{ .div = 4, .freq = 200 * MHZ },
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{ } /* sentinel */
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};
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static const struct mtk_pll_data plls[] = {
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PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
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HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
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0x0204, 0, 0, armpll_div_table),
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PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
|
||||
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
|
||||
0x0214, 0, 0, armpll_div_table),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
|
||||
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
|
||||
0x0294, 0, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
|
||||
0x0224, 0, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
|
||||
0x0234, 0, 0),
|
||||
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0,
|
||||
0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
|
||||
mfgpll_div_table),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
|
||||
0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
|
||||
0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
|
||||
HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
|
||||
0x0274, 0, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
|
||||
0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
|
||||
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
|
||||
};
|
||||
|
||||
static u16 infra_rst_ofs[] = {
|
||||
INFRA_RST0_SET_OFFSET,
|
||||
INFRA_RST1_SET_OFFSET,
|
||||
@ -1088,21 +953,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
|
||||
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct clk_hw_onecell_data *top_clk_data;
|
||||
|
||||
static void clk_mt8183_top_init_early(struct device_node *node)
|
||||
@ -1204,9 +1054,6 @@ static int clk_mt8183_mcu_probe(struct platform_device *pdev)
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8183-apmixedsys",
|
||||
.data = clk_mt8183_apmixed_probe,
|
||||
}, {
|
||||
.compatible = "mediatek,mt8183-topckgen",
|
||||
.data = clk_mt8183_top_probe,
|
||||
}, {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user