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[media] v4l: omap4iss: Create and use register access functions
Replace the direct readl/writel calls with helper functions that take an ISS pointer and compute the register memory address. Also add bit clear, set and update helpers. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
1be9ba20e1
commit
11abbfd30f
@ -32,7 +32,7 @@
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#define ISS_PRINT_REGISTER(iss, name)\
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dev_dbg(iss->dev, "###ISS " #name "=0x%08x\n", \
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readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_##name))
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iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_##name))
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static void iss_print_status(struct iss_device *iss)
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{
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@ -62,8 +62,8 @@ static void iss_print_status(struct iss_device *iss)
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*/
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void omap4iss_flush(struct iss_device *iss)
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{
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writel(0, iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_REVISION);
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readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_REVISION);
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION, 0);
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iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION);
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}
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/*
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@ -75,8 +75,8 @@ static void iss_enable_interrupts(struct iss_device *iss)
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static const u32 hl_irq = ISS_HL_IRQ_CSIA | ISS_HL_IRQ_CSIB | ISS_HL_IRQ_ISP(0);
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/* Enable HL interrupts */
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writel(hl_irq, iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_IRQSTATUS(5));
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writel(hl_irq, iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_IRQENABLE_SET(5));
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5), hl_irq);
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQENABLE_SET(5), hl_irq);
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}
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@ -86,7 +86,7 @@ static void iss_enable_interrupts(struct iss_device *iss)
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*/
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static void iss_disable_interrupts(struct iss_device *iss)
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{
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writel(-1, iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_IRQENABLE_CLR(5));
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQENABLE_CLR(5), -1);
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}
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/*
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@ -102,8 +102,9 @@ void omap4iss_isp_enable_interrupts(struct iss_device *iss)
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ISP5_IRQ_ISIF_INT(0);
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/* Enable ISP interrupts */
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writel(isp_irq, iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_IRQSTATUS(0));
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writel(isp_irq, iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_IRQENABLE_SET(0));
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQSTATUS(0), isp_irq);
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQENABLE_SET(0),
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isp_irq);
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}
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/*
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@ -112,7 +113,7 @@ void omap4iss_isp_enable_interrupts(struct iss_device *iss)
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*/
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void omap4iss_isp_disable_interrupts(struct iss_device *iss)
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{
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writel(-1, iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_IRQENABLE_CLR(0));
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQENABLE_CLR(0), -1);
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}
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int omap4iss_get_external_info(struct iss_pipeline *pipe,
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@ -169,11 +170,11 @@ void omap4iss_configure_bridge(struct iss_device *iss,
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u32 issctrl_val;
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u32 isp5ctrl_val;
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issctrl_val = readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_CTRL);
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issctrl_val = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_CTRL);
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issctrl_val &= ~ISS_CTRL_INPUT_SEL_MASK;
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issctrl_val &= ~ISS_CTRL_CLK_DIV_MASK;
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isp5ctrl_val = readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL);
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isp5ctrl_val = iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL);
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switch (input) {
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case IPIPEIF_INPUT_CSI2A:
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@ -193,8 +194,8 @@ void omap4iss_configure_bridge(struct iss_device *iss,
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isp5ctrl_val |= ISP5_CTRL_VD_PULSE_EXT | ISP5_CTRL_PSYNC_CLK_SEL |
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ISP5_CTRL_SYNC_ENABLE;
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writel(issctrl_val, iss->regs[OMAP4_ISS_MEM_TOP] + ISS_CTRL);
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writel(isp5ctrl_val, iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL);
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_CTRL, issctrl_val);
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, isp5ctrl_val);
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}
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#if defined(DEBUG) && defined(ISS_ISR_DEBUG)
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@ -313,8 +314,8 @@ static irqreturn_t iss_isr(int irq, void *_iss)
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struct iss_device *iss = _iss;
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u32 irqstatus;
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irqstatus = readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_IRQSTATUS(5));
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writel(irqstatus, iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_IRQSTATUS(5));
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irqstatus = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5));
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5), irqstatus);
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if (irqstatus & ISS_HL_IRQ_CSIA)
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omap4iss_csi2_isr(&iss->csi2a);
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@ -323,10 +324,10 @@ static irqreturn_t iss_isr(int irq, void *_iss)
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omap4iss_csi2_isr(&iss->csi2b);
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if (irqstatus & ISS_HL_IRQ_ISP(0)) {
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u32 isp_irqstatus = readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] +
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ISP5_IRQSTATUS(0));
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writel(isp_irqstatus, iss->regs[OMAP4_ISS_MEM_ISP_SYS1] +
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ISP5_IRQSTATUS(0));
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u32 isp_irqstatus = iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1,
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ISP5_IRQSTATUS(0));
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQSTATUS(0),
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isp_irqstatus);
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if (isp_irqstatus & ISP5_IRQ_OCP_ERR)
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dev_dbg(iss->dev, "ISP5 OCP Error!\n");
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@ -689,12 +690,11 @@ static int iss_reset(struct iss_device *iss)
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{
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unsigned long timeout = 0;
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writel(readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_SYSCONFIG) |
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ISS_HL_SYSCONFIG_SOFTRESET,
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iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_SYSCONFIG);
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iss_reg_set(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG,
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ISS_HL_SYSCONFIG_SOFTRESET);
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while (readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_SYSCONFIG) &
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ISS_HL_SYSCONFIG_SOFTRESET) {
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while (iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG) &
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ISS_HL_SYSCONFIG_SOFTRESET) {
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if (timeout++ > 100) {
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dev_alert(iss->dev, "cannot reset ISS\n");
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return -ETIMEDOUT;
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@ -710,18 +710,15 @@ static int iss_isp_reset(struct iss_device *iss)
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unsigned long timeout = 0;
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/* Fist, ensure that the ISP is IDLE (no transactions happening) */
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writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_SYSCONFIG) &
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~ISP5_SYSCONFIG_STANDBYMODE_MASK) |
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ISP5_SYSCONFIG_STANDBYMODE_SMART,
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iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_SYSCONFIG);
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iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG,
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ISP5_SYSCONFIG_STANDBYMODE_MASK,
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ISP5_SYSCONFIG_STANDBYMODE_SMART);
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writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL) |
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ISP5_CTRL_MSTANDBY,
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iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL);
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iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, ISP5_CTRL_MSTANDBY);
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for (;;) {
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if (readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL) &
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ISP5_CTRL_MSTANDBY_WAIT)
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if (iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL) &
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ISP5_CTRL_MSTANDBY_WAIT)
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break;
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if (timeout++ > 1000) {
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dev_alert(iss->dev, "cannot set ISP5 to standby\n");
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@ -731,13 +728,12 @@ static int iss_isp_reset(struct iss_device *iss)
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}
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/* Now finally, do the reset */
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writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_SYSCONFIG) |
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ISP5_SYSCONFIG_SOFTRESET,
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iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_SYSCONFIG);
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iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG,
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ISP5_SYSCONFIG_SOFTRESET);
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timeout = 0;
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while (readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_SYSCONFIG) &
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ISP5_SYSCONFIG_SOFTRESET) {
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while (iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG) &
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ISP5_SYSCONFIG_SOFTRESET) {
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if (timeout++ > 1000) {
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dev_alert(iss->dev, "cannot reset ISP5\n");
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return -ETIMEDOUT;
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@ -848,15 +844,14 @@ static int __iss_subclk_update(struct iss_device *iss)
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if (iss->subclk_resources & OMAP4_ISS_SUBCLK_ISP)
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clk |= ISS_CLKCTRL_ISP;
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writel((readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_CLKCTRL) &
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~ISS_CLKCTRL_MASK) | clk,
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iss->regs[OMAP4_ISS_MEM_TOP] + ISS_CLKCTRL);
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iss_reg_update(iss, OMAP4_ISS_MEM_TOP, ISS_CLKCTRL,
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ISS_CLKCTRL_MASK, clk);
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/* Wait for HW assertion */
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while (--timeout > 0) {
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udelay(1);
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if ((readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_CLKSTAT) &
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ISS_CLKCTRL_MASK) == clk)
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if ((iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_CLKSTAT) &
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ISS_CLKCTRL_MASK) == clk)
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break;
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}
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@ -911,9 +906,8 @@ static void __iss_isp_subclk_update(struct iss_device *iss)
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if (clk)
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clk |= ISP5_CTRL_BL_CLK_ENABLE;
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writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL) &
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~ISS_ISP5_CLKCTRL_MASK) | clk,
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iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_CTRL);
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iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL,
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ISS_ISP5_CLKCTRL_MASK, clk);
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}
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void omap4iss_isp_subclk_enable(struct iss_device *iss,
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@ -1380,7 +1374,7 @@ static int iss_probe(struct platform_device *pdev)
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if (ret < 0)
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goto error_iss;
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iss->revision = readl(iss->regs[OMAP4_ISS_MEM_TOP] + ISS_HL_REVISION);
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iss->revision = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION);
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dev_info(iss->dev, "Revision %08x found\n", iss->revision);
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for (i = 1; i < OMAP4_ISS_MEM_LAST; i++) {
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@ -1390,9 +1384,9 @@ static int iss_probe(struct platform_device *pdev)
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}
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/* Configure BTE BW_LIMITER field to max recommended value (1 GB) */
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writel((readl(iss->regs[OMAP4_ISS_MEM_BTE] + BTE_CTRL) & ~BTE_CTRL_BW_LIMITER_MASK) |
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(18 << BTE_CTRL_BW_LIMITER_SHIFT),
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iss->regs[OMAP4_ISS_MEM_BTE] + BTE_CTRL);
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iss_reg_update(iss, OMAP4_ISS_MEM_BTE, BTE_CTRL,
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BTE_CTRL_BW_LIMITER_MASK,
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18 << BTE_CTRL_BW_LIMITER_SHIFT);
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/* Perform ISP reset */
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ret = omap4iss_subclk_enable(iss, OMAP4_ISS_SUBCLK_ISP);
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@ -1404,7 +1398,7 @@ static int iss_probe(struct platform_device *pdev)
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goto error_iss;
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dev_info(iss->dev, "ISP Revision %08x found\n",
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readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_REVISION));
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iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_REVISION));
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/* Interrupt */
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iss->irq_num = platform_get_irq(pdev, 0);
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@ -150,4 +150,84 @@ int omap4iss_register_entities(struct platform_device *pdev,
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struct v4l2_device *v4l2_dev);
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void omap4iss_unregister_entities(struct platform_device *pdev);
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/*
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* iss_reg_read - Read the value of an OMAP4 ISS register
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* @iss: the ISS device
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* @res: memory resource in which the register is located
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* @offset: register offset in the memory resource
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*
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* Return the register value.
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*/
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static inline
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u32 iss_reg_read(struct iss_device *iss, enum iss_mem_resources res,
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u32 offset)
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{
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return readl(iss->regs[res] + offset);
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}
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/*
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* iss_reg_write - Write a value to an OMAP4 ISS register
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* @iss: the ISS device
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* @res: memory resource in which the register is located
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* @offset: register offset in the memory resource
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* @value: value to be written
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*/
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static inline
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void iss_reg_write(struct iss_device *iss, enum iss_mem_resources res,
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u32 offset, u32 value)
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{
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writel(value, iss->regs[res] + offset);
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}
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/*
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* iss_reg_clr - Clear bits in an OMAP4 ISS register
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* @iss: the ISS device
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* @res: memory resource in which the register is located
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* @offset: register offset in the memory resource
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* @clr: bit mask to be cleared
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*/
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static inline
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void iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res,
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u32 offset, u32 clr)
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{
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u32 v = iss_reg_read(iss, res, offset);
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iss_reg_write(iss, res, offset, v & ~clr);
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}
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/*
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* iss_reg_set - Set bits in an OMAP4 ISS register
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* @iss: the ISS device
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* @res: memory resource in which the register is located
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* @offset: register offset in the memory resource
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* @set: bit mask to be set
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*/
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static inline
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void iss_reg_set(struct iss_device *iss, enum iss_mem_resources res,
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u32 offset, u32 set)
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{
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u32 v = iss_reg_read(iss, res, offset);
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iss_reg_write(iss, res, offset, v | set);
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}
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/*
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* iss_reg_update - Clear and set bits in an OMAP4 ISS register
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* @iss: the ISS device
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* @res: memory resource in which the register is located
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* @offset: register offset in the memory resource
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* @clr: bit mask to be cleared
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* @set: bit mask to be set
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*
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* Clear the clr mask first and then set the set mask.
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*/
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static inline
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void iss_reg_update(struct iss_device *iss, enum iss_mem_resources res,
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u32 offset, u32 clr, u32 set)
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{
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u32 v = iss_reg_read(iss, res, offset);
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iss_reg_write(iss, res, offset, (v & ~clr) | set);
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}
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#endif /* _OMAP4_ISS_H_ */
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@ -42,7 +42,7 @@ static const unsigned int ipipe_fmts[] = {
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*/
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#define IPIPE_PRINT_REGISTER(iss, name)\
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dev_dbg(iss->dev, "###IPIPE " #name "=0x%08x\n", \
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readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_##name))
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iss_reg_read(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_##name))
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static void ipipe_print_status(struct iss_ipipe_device *ipipe)
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{
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@ -73,10 +73,8 @@ static void ipipe_enable(struct iss_ipipe_device *ipipe, u8 enable)
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{
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struct iss_device *iss = to_iss_device(ipipe);
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writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_EN) &
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~IPIPE_SRC_EN_EN) |
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(enable ? IPIPE_SRC_EN_EN : 0),
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iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_EN);
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iss_reg_update(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_EN,
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IPIPE_SRC_EN_EN, enable ? IPIPE_SRC_EN_EN : 0);
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}
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/* -----------------------------------------------------------------------------
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@ -92,31 +90,28 @@ static void ipipe_configure(struct iss_ipipe_device *ipipe)
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format = &ipipe->formats[IPIPE_PAD_SINK];
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/* NOTE: Currently just supporting pipeline IN: RGB, OUT: YUV422 */
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writel(IPIPE_SRC_FMT_RAW2YUV,
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iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_FMT);
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_FMT,
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IPIPE_SRC_FMT_RAW2YUV);
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/* Enable YUV444 -> YUV422 conversion */
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writel(IPIPE_YUV_PHS_LPF,
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iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_YUV_PHS);
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_YUV_PHS,
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IPIPE_YUV_PHS_LPF);
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|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_VPS);
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_HPS);
|
||||
writel((format->height - 2) & IPIPE_SRC_VSZ_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_VSZ);
|
||||
writel((format->width - 1) & IPIPE_SRC_HSZ_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_HSZ);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_VPS, 0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_HPS, 0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_VSZ,
|
||||
(format->height - 2) & IPIPE_SRC_VSZ_MASK);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_HSZ,
|
||||
(format->width - 1) & IPIPE_SRC_HSZ_MASK);
|
||||
|
||||
/* Ignore ipipeif_wrt signal, and operate on-the-fly. */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_MODE) &
|
||||
~(IPIPE_SRC_MODE_WRT | IPIPE_SRC_MODE_OST),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_MODE);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_MODE,
|
||||
IPIPE_SRC_MODE_WRT | IPIPE_SRC_MODE_OST);
|
||||
|
||||
/* HACK: Values tuned for Ducati SW (OV) */
|
||||
writel(IPIPE_SRC_COL_EE_B |
|
||||
IPIPE_SRC_COL_EO_GB |
|
||||
IPIPE_SRC_COL_OE_GR |
|
||||
IPIPE_SRC_COL_OO_R,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_COL);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_COL,
|
||||
IPIPE_SRC_COL_EE_B | IPIPE_SRC_COL_EO_GB |
|
||||
IPIPE_SRC_COL_OE_GR | IPIPE_SRC_COL_OO_R);
|
||||
|
||||
/* IPIPE_PAD_SOURCE_VP */
|
||||
format = &ipipe->formats[IPIPE_PAD_SOURCE_VP];
|
||||
@ -147,15 +142,13 @@ static int ipipe_set_stream(struct v4l2_subdev *sd, int enable)
|
||||
omap4iss_isp_subclk_enable(iss, OMAP4_ISS_ISP_SUBCLK_IPIPE);
|
||||
|
||||
/* Enable clk_arm_g0 */
|
||||
writel(IPIPE_GCK_MMR_REG,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_GCK_MMR);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_GCK_MMR,
|
||||
IPIPE_GCK_MMR_REG);
|
||||
|
||||
/* Enable clk_pix_g[3:0] */
|
||||
writel(IPIPE_GCK_PIX_G3 |
|
||||
IPIPE_GCK_PIX_G2 |
|
||||
IPIPE_GCK_PIX_G1 |
|
||||
IPIPE_GCK_PIX_G0,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_GCK_PIX);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_GCK_PIX,
|
||||
IPIPE_GCK_PIX_G3 | IPIPE_GCK_PIX_G2 |
|
||||
IPIPE_GCK_PIX_G1 | IPIPE_GCK_PIX_G0);
|
||||
}
|
||||
|
||||
switch (enable) {
|
||||
|
||||
@ -40,15 +40,15 @@ static const unsigned int ipipeif_fmts[] = {
|
||||
*/
|
||||
#define IPIPEIF_PRINT_REGISTER(iss, name)\
|
||||
dev_dbg(iss->dev, "###IPIPEIF " #name "=0x%08x\n", \
|
||||
readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_##name))
|
||||
iss_reg_read(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_##name))
|
||||
|
||||
#define ISIF_PRINT_REGISTER(iss, name)\
|
||||
dev_dbg(iss->dev, "###ISIF " #name "=0x%08x\n", \
|
||||
readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_##name))
|
||||
iss_reg_read(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_##name))
|
||||
|
||||
#define ISP5_PRINT_REGISTER(iss, name)\
|
||||
dev_dbg(iss->dev, "###ISP5 " #name "=0x%08x\n", \
|
||||
readl(iss->regs[OMAP4_ISS_MEM_ISP_SYS1] + ISP5_##name))
|
||||
iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_##name))
|
||||
|
||||
static void ipipeif_print_status(struct iss_ipipeif_device *ipipeif)
|
||||
{
|
||||
@ -83,10 +83,8 @@ static void ipipeif_write_enable(struct iss_ipipeif_device *ipipeif, u8 enable)
|
||||
{
|
||||
struct iss_device *iss = to_iss_device(ipipeif);
|
||||
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN) &
|
||||
~ISIF_SYNCEN_DWEN) |
|
||||
(enable ? ISIF_SYNCEN_DWEN : 0),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_SYNCEN,
|
||||
ISIF_SYNCEN_DWEN, enable ? ISIF_SYNCEN_DWEN : 0);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -98,10 +96,8 @@ static void ipipeif_enable(struct iss_ipipeif_device *ipipeif, u8 enable)
|
||||
{
|
||||
struct iss_device *iss = to_iss_device(ipipeif);
|
||||
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN) &
|
||||
~ISIF_SYNCEN_SYEN) |
|
||||
(enable ? ISIF_SYNCEN_SYEN : 0),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_SYNCEN,
|
||||
ISIF_SYNCEN_SYEN, enable ? ISIF_SYNCEN_SYEN : 0);
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
@ -120,10 +116,10 @@ static void ipipeif_set_outaddr(struct iss_ipipeif_device *ipipeif, u32 addr)
|
||||
struct iss_device *iss = to_iss_device(ipipeif);
|
||||
|
||||
/* Save address splitted in Base Address H & L */
|
||||
writel((addr >> (16 + 5)) & ISIF_CADU_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_CADU);
|
||||
writel((addr >> 5) & ISIF_CADL_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_CADL);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CADU,
|
||||
(addr >> (16 + 5)) & ISIF_CADU_MASK);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CADL,
|
||||
(addr >> 5) & ISIF_CADL_MASK);
|
||||
}
|
||||
|
||||
static void ipipeif_configure(struct iss_ipipeif_device *ipipeif)
|
||||
@ -139,25 +135,20 @@ static void ipipeif_configure(struct iss_ipipeif_device *ipipeif)
|
||||
format = &ipipeif->formats[IPIPEIF_PAD_SINK];
|
||||
|
||||
/* IPIPEIF with YUV422 input from ISIF */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_CFG1) &
|
||||
~(IPIPEIF_CFG1_INPSRC1_MASK | IPIPEIF_CFG1_INPSRC2_MASK),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_CFG1);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_CFG1,
|
||||
IPIPEIF_CFG1_INPSRC1_MASK | IPIPEIF_CFG1_INPSRC2_MASK);
|
||||
|
||||
/* Select ISIF/IPIPEIF input format */
|
||||
switch (format->code) {
|
||||
case V4L2_MBUS_FMT_UYVY8_1X16:
|
||||
case V4L2_MBUS_FMT_YUYV8_1X16:
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_MODESET) &
|
||||
~(ISIF_MODESET_CCDMD |
|
||||
ISIF_MODESET_INPMOD_MASK |
|
||||
ISIF_MODESET_CCDW_MASK)) |
|
||||
ISIF_MODESET_INPMOD_YCBCR16,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_MODESET);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_MODESET,
|
||||
ISIF_MODESET_CCDMD | ISIF_MODESET_INPMOD_MASK |
|
||||
ISIF_MODESET_CCDW_MASK,
|
||||
ISIF_MODESET_INPMOD_YCBCR16);
|
||||
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_CFG2) &
|
||||
~IPIPEIF_CFG2_YUV8) |
|
||||
IPIPEIF_CFG2_YUV16,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_CFG2);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_CFG2,
|
||||
IPIPEIF_CFG2_YUV8, IPIPEIF_CFG2_YUV16);
|
||||
|
||||
break;
|
||||
case V4L2_MBUS_FMT_SGRBG10_1X10:
|
||||
@ -184,44 +175,41 @@ static void ipipeif_configure(struct iss_ipipeif_device *ipipeif)
|
||||
ISIF_CCOLP_CP2_F0_R |
|
||||
ISIF_CCOLP_CP3_F0_GR;
|
||||
cont_raw:
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_CFG2) &
|
||||
~IPIPEIF_CFG2_YUV16),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_IPIPEIF] + IPIPEIF_CFG2);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_CFG2,
|
||||
IPIPEIF_CFG2_YUV16);
|
||||
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_MODESET) &
|
||||
~(ISIF_MODESET_CCDMD |
|
||||
ISIF_MODESET_INPMOD_MASK |
|
||||
ISIF_MODESET_CCDW_MASK)) |
|
||||
ISIF_MODESET_INPMOD_RAW | ISIF_MODESET_CCDW_2BIT,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_MODESET);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_MODESET,
|
||||
ISIF_MODESET_CCDMD | ISIF_MODESET_INPMOD_MASK |
|
||||
ISIF_MODESET_CCDW_MASK, ISIF_MODESET_INPMOD_RAW |
|
||||
ISIF_MODESET_CCDW_2BIT);
|
||||
|
||||
info = omap4iss_video_format_info(format->code);
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_CGAMMAWD) &
|
||||
~ISIF_CGAMMAWD_GWDI_MASK) |
|
||||
ISIF_CGAMMAWD_GWDI(info->bpp),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_CGAMMAWD);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CGAMMAWD,
|
||||
ISIF_CGAMMAWD_GWDI_MASK,
|
||||
ISIF_CGAMMAWD_GWDI(info->bpp));
|
||||
|
||||
/* Set RAW Bayer pattern */
|
||||
writel(isif_ccolp,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_CCOLP);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CCOLP,
|
||||
isif_ccolp);
|
||||
break;
|
||||
}
|
||||
|
||||
writel(0 & ISIF_SPH_MASK, iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SPH);
|
||||
writel((format->width - 1) & ISIF_LNH_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_LNH);
|
||||
writel((format->height - 1) & ISIF_LNV_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_LNV);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_SPH, 0 & ISIF_SPH_MASK);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_LNH,
|
||||
(format->width - 1) & ISIF_LNH_MASK);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_LNV,
|
||||
(format->height - 1) & ISIF_LNV_MASK);
|
||||
|
||||
/* Generate ISIF0 on the last line of the image */
|
||||
writel(format->height - 1,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_VDINT(0));
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_VDINT(0),
|
||||
format->height - 1);
|
||||
|
||||
/* IPIPEIF_PAD_SOURCE_ISIF_SF */
|
||||
format = &ipipeif->formats[IPIPEIF_PAD_SOURCE_ISIF_SF];
|
||||
|
||||
writel((ipipeif->video_out.bpl_value >> 5) & ISIF_HSIZE_HSIZE_MASK,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_HSIZE);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_HSIZE,
|
||||
(ipipeif->video_out.bpl_value >> 5) &
|
||||
ISIF_HSIZE_HSIZE_MASK);
|
||||
|
||||
/* IPIPEIF_PAD_SOURCE_VP */
|
||||
/* Do nothing? */
|
||||
|
||||
@ -36,11 +36,11 @@ static const unsigned int resizer_fmts[] = {
|
||||
*/
|
||||
#define RSZ_PRINT_REGISTER(iss, name)\
|
||||
dev_dbg(iss->dev, "###RSZ " #name "=0x%08x\n", \
|
||||
readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_##name))
|
||||
iss_reg_read(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_##name))
|
||||
|
||||
#define RZA_PRINT_REGISTER(iss, name)\
|
||||
dev_dbg(iss->dev, "###RZA " #name "=0x%08x\n", \
|
||||
readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_##name))
|
||||
iss_reg_read(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_##name))
|
||||
|
||||
static void resizer_print_status(struct iss_resizer_device *resizer)
|
||||
{
|
||||
@ -116,16 +116,12 @@ static void resizer_enable(struct iss_resizer_device *resizer, u8 enable)
|
||||
{
|
||||
struct iss_device *iss = to_iss_device(resizer);
|
||||
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN) &
|
||||
~RSZ_SRC_EN_SRC_EN) |
|
||||
(enable ? RSZ_SRC_EN_SRC_EN : 0),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_EN,
|
||||
RSZ_SRC_EN_SRC_EN, enable ? RSZ_SRC_EN_SRC_EN : 0);
|
||||
|
||||
/* TODO: Enable RSZB */
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) &
|
||||
~RSZ_EN_EN) |
|
||||
(enable ? RSZ_EN_EN : 0),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_EN, RSZ_EN_EN,
|
||||
enable ? RSZ_EN_EN : 0);
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
@ -148,16 +144,16 @@ static void resizer_set_outaddr(struct iss_resizer_device *resizer, u32 addr)
|
||||
outformat = &resizer->formats[RESIZER_PAD_SOURCE_MEM];
|
||||
|
||||
/* Save address splitted in Base Address H & L */
|
||||
writel((addr >> 16) & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_BAD_H);
|
||||
writel(addr & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_BAD_L);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_BAD_H,
|
||||
(addr >> 16) & 0xffff);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_BAD_L,
|
||||
addr & 0xffff);
|
||||
|
||||
/* SAD = BAD */
|
||||
writel((addr >> 16) & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_SAD_H);
|
||||
writel(addr & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_SAD_L);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_SAD_H,
|
||||
(addr >> 16) & 0xffff);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_SAD_L,
|
||||
addr & 0xffff);
|
||||
|
||||
/* Program UV buffer address... Hardcoded to be contiguous! */
|
||||
if ((informat->code == V4L2_MBUS_FMT_UYVY8_1X16) &&
|
||||
@ -173,16 +169,16 @@ static void resizer_set_outaddr(struct iss_resizer_device *resizer, u32 addr)
|
||||
}
|
||||
|
||||
/* Save address splitted in Base Address H & L */
|
||||
writel((c_addr >> 16) & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_BAD_H);
|
||||
writel(c_addr & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_BAD_L);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_BAD_H,
|
||||
(c_addr >> 16) & 0xffff);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_BAD_L,
|
||||
c_addr & 0xffff);
|
||||
|
||||
/* SAD = BAD */
|
||||
writel((c_addr >> 16) & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_SAD_H);
|
||||
writel(c_addr & 0xffff,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_SAD_L);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_SAD_H,
|
||||
(c_addr >> 16) & 0xffff);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_SAD_L,
|
||||
c_addr & 0xffff);
|
||||
}
|
||||
}
|
||||
|
||||
@ -195,70 +191,70 @@ static void resizer_configure(struct iss_resizer_device *resizer)
|
||||
outformat = &resizer->formats[RESIZER_PAD_SOURCE_MEM];
|
||||
|
||||
/* Make sure we don't bypass the resizer */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0) &
|
||||
~RSZ_SRC_FMT0_BYPASS,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_FMT0,
|
||||
RSZ_SRC_FMT0_BYPASS);
|
||||
|
||||
/* Select RSZ input */
|
||||
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0) &
|
||||
~RSZ_SRC_FMT0_SEL) |
|
||||
(resizer->input == RESIZER_INPUT_IPIPEIF ? RSZ_SRC_FMT0_SEL : 0),
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0);
|
||||
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_FMT0,
|
||||
RSZ_SRC_FMT0_SEL,
|
||||
resizer->input == RESIZER_INPUT_IPIPEIF ?
|
||||
RSZ_SRC_FMT0_SEL : 0);
|
||||
|
||||
/* RSZ ignores WEN signal from IPIPE/IPIPEIF */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE) &
|
||||
~RSZ_SRC_MODE_WRT,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_MODE,
|
||||
RSZ_SRC_MODE_WRT);
|
||||
|
||||
/* Set Resizer in free-running mode */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE) &
|
||||
~RSZ_SRC_MODE_OST,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_MODE,
|
||||
RSZ_SRC_MODE_OST);
|
||||
|
||||
/* Init Resizer A */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_MODE) &
|
||||
~RZA_MODE_ONE_SHOT,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_MODE);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_MODE,
|
||||
RZA_MODE_ONE_SHOT);
|
||||
|
||||
/* Set size related things now */
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_VPS);
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_HPS);
|
||||
writel(informat->height - 2, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_VSZ);
|
||||
writel(informat->width - 1, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_HSZ);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_VPS, 0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_HPS, 0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_VSZ,
|
||||
informat->height - 2);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SRC_HSZ,
|
||||
informat->width - 1);
|
||||
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_I_VPS);
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_I_HPS);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_I_VPS, 0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_I_HPS, 0);
|
||||
|
||||
writel(outformat->height - 2, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_O_VSZ);
|
||||
writel(outformat->width - 1, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_O_HSZ);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_O_VSZ,
|
||||
outformat->height - 2);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_O_HSZ,
|
||||
outformat->width - 1);
|
||||
|
||||
writel(0x100, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_V_DIF);
|
||||
writel(0x100, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_H_DIF);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_V_DIF, 0x100);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_H_DIF, 0x100);
|
||||
|
||||
/* Buffer output settings */
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_PTR_S);
|
||||
writel(outformat->height - 1,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_PTR_E);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_PTR_S, 0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_PTR_E,
|
||||
outformat->height - 1);
|
||||
|
||||
writel(resizer->video_out.bpl_value,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_OFT);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_OFT,
|
||||
resizer->video_out.bpl_value);
|
||||
|
||||
/* UYVY -> NV12 conversion */
|
||||
if ((informat->code == V4L2_MBUS_FMT_UYVY8_1X16) &&
|
||||
(outformat->code == V4L2_MBUS_FMT_YUYV8_1_5X8)) {
|
||||
writel(RSZ_420_CEN | RSZ_420_YEN,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_420);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_420,
|
||||
RSZ_420_CEN | RSZ_420_YEN);
|
||||
|
||||
/* UV Buffer output settings */
|
||||
writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_PTR_S);
|
||||
writel(outformat->height - 1,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_PTR_E);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_PTR_S,
|
||||
0);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_PTR_E,
|
||||
outformat->height - 1);
|
||||
|
||||
writel(resizer->video_out.bpl_value,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_OFT);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_OFT,
|
||||
resizer->video_out.bpl_value);
|
||||
} else {
|
||||
writel(0,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_420);
|
||||
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_420, 0);
|
||||
}
|
||||
|
||||
omap4iss_isp_enable_interrupts(iss);
|
||||
@ -273,9 +269,7 @@ static void resizer_isr_buffer(struct iss_resizer_device *resizer)
|
||||
struct iss_device *iss = to_iss_device(resizer);
|
||||
struct iss_buffer *buffer;
|
||||
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) &
|
||||
~RSZ_EN_EN,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_EN, RSZ_EN_EN);
|
||||
|
||||
buffer = omap4iss_video_buffer_next(&resizer->video_out);
|
||||
if (buffer == NULL)
|
||||
@ -283,9 +277,7 @@ static void resizer_isr_buffer(struct iss_resizer_device *resizer)
|
||||
|
||||
resizer_set_outaddr(resizer, buffer->iss_addr);
|
||||
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) |
|
||||
RSZ_EN_EN,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN);
|
||||
iss_reg_set(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_EN, RSZ_EN_EN);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -386,17 +378,14 @@ static int resizer_set_stream(struct v4l2_subdev *sd, int enable)
|
||||
|
||||
omap4iss_isp_subclk_enable(iss, OMAP4_ISS_ISP_SUBCLK_RSZ);
|
||||
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR) |
|
||||
RSZ_GCK_MMR_MMR,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR);
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR) |
|
||||
RSZ_GCK_SDR_CORE,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR);
|
||||
iss_reg_set(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_GCK_MMR,
|
||||
RSZ_GCK_MMR_MMR);
|
||||
iss_reg_set(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_GCK_SDR,
|
||||
RSZ_GCK_SDR_CORE);
|
||||
|
||||
/* FIXME: Enable RSZB also */
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG) |
|
||||
RSZ_SYSCONFIG_RSZA_CLK_EN,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG);
|
||||
iss_reg_set(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SYSCONFIG,
|
||||
RSZ_SYSCONFIG_RSZA_CLK_EN);
|
||||
}
|
||||
|
||||
switch (enable) {
|
||||
@ -430,15 +419,12 @@ static int resizer_set_stream(struct v4l2_subdev *sd, int enable)
|
||||
|
||||
resizer_enable(resizer, 0);
|
||||
omap4iss_isp_disable_interrupts(iss);
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG) &
|
||||
~RSZ_SYSCONFIG_RSZA_CLK_EN,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG);
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR) &
|
||||
~RSZ_GCK_SDR_CORE,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR);
|
||||
writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR) &
|
||||
~RSZ_GCK_MMR_MMR,
|
||||
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_SYSCONFIG,
|
||||
RSZ_SYSCONFIG_RSZA_CLK_EN);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_GCK_SDR,
|
||||
RSZ_GCK_SDR_CORE);
|
||||
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_RESIZER, RSZ_GCK_MMR,
|
||||
RSZ_GCK_MMR_MMR);
|
||||
omap4iss_isp_subclk_disable(iss, OMAP4_ISS_ISP_SUBCLK_RSZ);
|
||||
iss_video_dmaqueue_flags_clr(video_out);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user