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RDMA/mlx5: Add DCS offload support

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DCS is an offload to SW load balancing of DC initiator work requests.

A single DCI can be connected to only one target at the time and can't
start new connection until the previous work request is completed.  This
limitation will cause to delay when the initiator process needs to
transfer data to multiple targets at the same time.  The SW solution is to
use a process that handling and spreading the work request on many DCIs
according to destinations.

This feature is an offload to this process and coming to reduce the load
from the CPU and improve the performance.

Link: https://lore.kernel.org/r/491c2c2afdb5b07de7f03eab3f93cf0704549dbc.1624258894.git.leonro@nvidia.com
Reviewed-by: Meir Lichtinger <meirl@nvidia.com>
Signed-off-by: Lior Nahmanson <liorna@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Lior Nahmanson 2021-06-21 10:06:16 +03:00 committed by Jason Gunthorpe
parent 2013b4d525
commit 11656f593a
3 changed files with 36 additions and 2 deletions
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10
drivers/infiniband/hw/mlx5/main.c
View File

@ -1174,6 +1174,16 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
}
if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
resp.response_length += sizeof(resp.dci_streams_caps);
resp.dci_streams_caps.max_log_num_concurent =
MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
resp.dci_streams_caps.max_log_num_errored =
MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
}
if (uhw_outlen) {
err = ib_copy_to_udata(uhw, &resp, resp.response_length);

11
drivers/infiniband/hw/mlx5/qp.c
View File

@ -2064,6 +2064,13 @@ static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd,
MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
}
if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) {
MLX5_SET(qpc, qpc, log_num_dci_stream_channels,
ucmd->dci_streams.log_num_concurent);
MLX5_SET(qpc, qpc, log_num_dci_errored_streams,
ucmd->dci_streams.log_num_errored);
}
MLX5_SET(qpc, qpc, ts_format, ts_format);
MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
@ -2807,6 +2814,10 @@ static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM,
MLX5_CAP_GEN(mdev, log_max_dci_stream_channels) &&
MLX5_CAP_GEN(mdev, log_max_dci_errored_streams),
qp);
process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,

17
include/uapi/rdma/mlx5-abi.h
View File

@ -50,6 +50,7 @@ enum {
MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
MLX5_QP_FLAG_DCI_STREAM = 1 << 11,
};
enum {
@ -238,6 +239,11 @@ struct mlx5_ib_striding_rq_caps {
__u32 reserved;
};
struct mlx5_ib_dci_streams_caps {
__u8 max_log_num_concurent;
__u8 max_log_num_errored;
};
enum mlx5_ib_query_dev_resp_flags {
/* Support 128B CQE compression */
MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
@ -266,7 +272,8 @@ struct mlx5_ib_query_device_resp {
struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
struct mlx5_ib_striding_rq_caps striding_rq_caps;
__u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
__u32 reserved;
struct mlx5_ib_dci_streams_caps dci_streams_caps;
__u16 reserved;
};
enum mlx5_ib_create_cq_flags {
@ -313,6 +320,11 @@ struct mlx5_ib_create_srq_resp {
__u32 reserved;
};
struct mlx5_ib_create_qp_dci_streams {
__u8 log_num_concurent;
__u8 log_num_errored;
};
struct mlx5_ib_create_qp {
__aligned_u64 buf_addr;
__aligned_u64 db_addr;
@ -327,7 +339,8 @@ struct mlx5_ib_create_qp {
__aligned_u64 access_key;
};
__u32 ece_options;
__u32 reserved;
struct mlx5_ib_create_qp_dci_streams dci_streams;
__u16 reserved;
};
/* RX Hash function flags */