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bitops: Introduce a more generic BITMASK macro
GENMASK is used to create a contiguous bitmask([hi:lo]). It is implemented twice in current kernel. One is in EDAC driver, the other is in SiS/XGI FB driver. Move it to a more generic place for other usage. Signed-off-by: Chen, Gong <gong.chen@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Thomas Winischhofer <thomas@winischhofer.net> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Borislav Petkov <bp@suse.de> Acked-by: Mauro Carvalho Chehab <m.chehab@samsung.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Chen, Gong
Tony Luck
parent
88f074f487
commit
10ef6b0dff
@ -339,8 +339,8 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
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if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
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csbase = pvt->csels[dct].csbases[csrow];
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csmask = pvt->csels[dct].csmasks[csrow];
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base_bits = GENMASK(21, 31) | GENMASK(9, 15);
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mask_bits = GENMASK(21, 29) | GENMASK(9, 15);
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base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
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mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
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addr_shift = 4;
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/*
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@ -352,16 +352,16 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
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csbase = pvt->csels[dct].csbases[csrow];
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csmask = pvt->csels[dct].csmasks[csrow >> 1];
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*base = (csbase & GENMASK(5, 15)) << 6;
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*base |= (csbase & GENMASK(19, 30)) << 8;
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*base = (csbase & GENMASK_ULL(15, 5)) << 6;
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*base |= (csbase & GENMASK_ULL(30, 19)) << 8;
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*mask = ~0ULL;
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/* poke holes for the csmask */
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*mask &= ~((GENMASK(5, 15) << 6) |
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(GENMASK(19, 30) << 8));
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*mask &= ~((GENMASK_ULL(15, 5) << 6) |
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(GENMASK_ULL(30, 19) << 8));
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*mask |= (csmask & GENMASK(5, 15)) << 6;
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*mask |= (csmask & GENMASK(19, 30)) << 8;
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*mask |= (csmask & GENMASK_ULL(15, 5)) << 6;
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*mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
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return;
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} else {
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@ -370,9 +370,11 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
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addr_shift = 8;
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if (pvt->fam == 0x15)
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base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13);
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base_bits = mask_bits =
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GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
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else
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base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13);
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base_bits = mask_bits =
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GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
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}
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*base = (csbase & base_bits) << addr_shift;
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@ -561,7 +563,7 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
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* section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
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* Programmer's Manual Volume 1 Application Programming.
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*/
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dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;
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dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
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edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
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(unsigned long)sys_addr, (unsigned long)dram_addr);
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@ -597,7 +599,7 @@ static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
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* concerning translating a DramAddr to an InputAddr.
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*/
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intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
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input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +
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input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
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(dram_addr & 0xfff);
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edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
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@ -849,7 +851,7 @@ static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
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end_bit = 39;
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}
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addr = m->addr & GENMASK(start_bit, end_bit);
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addr = m->addr & GENMASK_ULL(end_bit, start_bit);
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/*
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* Erratum 637 workaround
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@ -861,7 +863,7 @@ static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
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u16 mce_nid;
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u8 intlv_en;
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if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
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if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
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return addr;
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mce_nid = amd_get_nb_id(m->extcpu);
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@ -871,7 +873,7 @@ static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
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intlv_en = tmp >> 21 & 0x7;
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/* add [47:27] + 3 trailing bits */
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cc6_base = (tmp & GENMASK(0, 20)) << 3;
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cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3;
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/* reverse and add DramIntlvEn */
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cc6_base |= intlv_en ^ 0x7;
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@ -880,18 +882,18 @@ static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
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cc6_base <<= 24;
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if (!intlv_en)
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return cc6_base | (addr & GENMASK(0, 23));
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return cc6_base | (addr & GENMASK_ULL(23, 0));
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amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
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/* faster log2 */
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tmp_addr = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1);
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tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
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/* OR DramIntlvSel into bits [14:12] */
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tmp_addr |= (tmp & GENMASK(21, 23)) >> 9;
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tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
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/* add remaining [11:0] bits from original MC4_ADDR */
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tmp_addr |= addr & GENMASK(0, 11);
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tmp_addr |= addr & GENMASK_ULL(11, 0);
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return cc6_base | tmp_addr;
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}
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@ -952,12 +954,12 @@ static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
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pvt->ranges[range].lim.lo &= GENMASK(0, 15);
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pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
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/* {[39:27],111b} */
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pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
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pvt->ranges[range].lim.hi &= GENMASK(0, 7);
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pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
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/* [47:40] */
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pvt->ranges[range].lim.hi |= llim >> 13;
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@ -1330,7 +1332,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
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chan_off = dram_base;
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}
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return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47));
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return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
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}
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/*
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@ -159,14 +159,6 @@
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#define ON true
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#define OFF false
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/*
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* Create a contiguous bitmask starting at bit position @lo and ending at
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* position @hi. For example
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*
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* GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
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*/
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#define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
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/*
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* PCI-defined configuration space registers
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*/
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@ -50,7 +50,7 @@ static int probed;
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* Get a bit field at register value <v>, from bit <lo> to bit <hi>
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*/
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#define GET_BITFIELD(v, lo, hi) \
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(((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
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(((v) & GENMASK_ULL(hi, lo)) >> (lo))
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/*
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* sbridge Memory Controller Registers
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@ -3320,9 +3320,8 @@ SiSSetMode(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
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}
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#ifndef GETBITSTR
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#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
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#define GENMASK(mask) BITMASK(1?mask,0?mask)
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#define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask))
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#define GENBITSMASK(mask) GENMASK(1?mask,0?mask)
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#define GETBITS(var,mask) (((var) & GENBITSMASK(mask)) >> (0?mask))
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#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
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#endif
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@ -10,6 +10,14 @@
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#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
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#endif
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/*
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* Create a contiguous bitmask starting at bit position @l and ending at
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* position @h. For example
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* GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
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*/
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#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
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#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l))
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extern unsigned int __sw_hweight8(unsigned int w);
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extern unsigned int __sw_hweight16(unsigned int w);
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extern unsigned int __sw_hweight32(unsigned int w);
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