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spi: sun6i: Support Allwinner H3 SPI controller
H3 has two SPI controllers. The size of the buffer is 64 * 8. (8 bit transfer by 64 entry FIFO) A31 has four controllers. The size of the buffer is 128 * 8. (8 bit transfer by 128 entry FIFO) Register maps are sharable, so sun6i SPI driver is reusable with device configuration. Use the variable, 'fifo_depth' instead of fixed value to support both SPI controllers. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
8ea7ce9cc6
commit
10565dfd35
@ -17,6 +17,7 @@
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/reset.h>
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@ -24,6 +25,7 @@
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#include <linux/spi/spi.h>
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#include <linux/spi/spi.h>
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#define SUN6I_FIFO_DEPTH 128
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#define SUN6I_FIFO_DEPTH 128
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#define SUN8I_FIFO_DEPTH 64
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
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@ -90,6 +92,7 @@ struct sun6i_spi {
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const u8 *tx_buf;
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const u8 *tx_buf;
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u8 *rx_buf;
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u8 *rx_buf;
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int len;
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int len;
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unsigned long fifo_depth;
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};
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};
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static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
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static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
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@ -155,7 +158,9 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
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static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
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static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
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{
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{
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return SUN6I_FIFO_DEPTH - 1;
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struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
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return sspi->fifo_depth - 1;
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}
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}
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static int sun6i_spi_transfer_one(struct spi_master *master,
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static int sun6i_spi_transfer_one(struct spi_master *master,
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@ -170,7 +175,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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u32 reg;
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u32 reg;
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/* We don't support transfer larger than the FIFO */
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN6I_FIFO_DEPTH)
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if (tfr->len > sspi->fifo_depth)
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return -EINVAL;
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return -EINVAL;
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reinit_completion(&sspi->done);
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reinit_completion(&sspi->done);
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@ -265,7 +270,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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SUN6I_BURST_CTL_CNT_STC(tx_len));
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SUN6I_BURST_CTL_CNT_STC(tx_len));
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/* Fill the TX FIFO */
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/* Fill the TX FIFO */
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sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
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sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
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/* Enable the interrupts */
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/* Enable the interrupts */
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
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@ -288,7 +293,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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goto out;
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goto out;
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}
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}
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sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
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sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
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out:
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out:
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
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@ -398,6 +403,8 @@ static int sun6i_spi_probe(struct platform_device *pdev)
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}
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}
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sspi->master = master;
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sspi->master = master;
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sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
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master->max_speed_hz = 100 * 1000 * 1000;
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master->max_speed_hz = 100 * 1000 * 1000;
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master->min_speed_hz = 3 * 1000;
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master->min_speed_hz = 3 * 1000;
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master->set_cs = sun6i_spi_set_cs;
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master->set_cs = sun6i_spi_set_cs;
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@ -470,7 +477,8 @@ static int sun6i_spi_remove(struct platform_device *pdev)
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}
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}
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static const struct of_device_id sun6i_spi_match[] = {
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static const struct of_device_id sun6i_spi_match[] = {
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{ .compatible = "allwinner,sun6i-a31-spi", },
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{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
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{ .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
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{}
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{}
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};
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};
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MODULE_DEVICE_TABLE(of, sun6i_spi_match);
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MODULE_DEVICE_TABLE(of, sun6i_spi_match);
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