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Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next

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This commit is contained in:
Mark Brown 2015-02-09 15:10:02 +08:00
commit 1030047492
5 changed files with 1139 additions and 24 deletions
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25
Documentation/devicetree/bindings/sound/pcm512x.txt
View File

@ -17,9 +17,16 @@ Required properties:
Optional properties:
- clocks : A clock specifier for the clock connected as SCLK. If this
is absent the device will be configured to clock from BCLK.
is absent the device will be configured to clock from BCLK. If pll-in
and pll-out are specified in addition to a clock, the device is
configured to accept clock input on a specified gpio pin.
Example:
- pll-in, pll-out : gpio pins used to connect the pll using <1>
through <6>. The device will be configured for clock input on the
given pll-in pin and PLL output on the given pll-out pin. An
external connection from the pll-out pin to the SCLK pin is assumed.
Examples:
pcm5122: pcm5122@4c {
compatible = "ti,pcm5122";
@ -29,3 +36,17 @@ Example:
DVDD-supply = <&reg_1v8>;
CPVDD-supply = <&reg_3v3>;
};
pcm5142: pcm5142@4c {
compatible = "ti,pcm5142";
reg = <0x4c>;
AVDD-supply = <&reg_3v3_analog>;
DVDD-supply = <&reg_1v8>;
CPVDD-supply = <&reg_3v3>;
clocks = <&sck>;
pll-in = <3>;
pll-out = <6>;
};

12
include/sound/pcm.h
View File

@ -275,6 +275,12 @@ struct snd_pcm_hw_constraint_list {
unsigned int mask;
};
struct snd_pcm_hw_constraint_ranges {
unsigned int count;
const struct snd_interval *ranges;
unsigned int mask;
};
struct snd_pcm_hwptr_log;
struct snd_pcm_runtime {
@ -910,6 +916,8 @@ void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k,
const struct snd_interval *b, struct snd_interval *c);
int snd_interval_list(struct snd_interval *i, unsigned int count,
const unsigned int *list, unsigned int mask);
int snd_interval_ranges(struct snd_interval *i, unsigned int count,
const struct snd_interval *list, unsigned int mask);
int snd_interval_ratnum(struct snd_interval *i,
unsigned int rats_count, struct snd_ratnum *rats,
unsigned int *nump, unsigned int *denp);
@ -934,6 +942,10 @@ int snd_pcm_hw_constraint_list(struct snd_pcm_runtime *runtime,
unsigned int cond,
snd_pcm_hw_param_t var,
const struct snd_pcm_hw_constraint_list *l);
int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime,
unsigned int cond,
snd_pcm_hw_param_t var,
const struct snd_pcm_hw_constraint_ranges *r);
int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime,
unsigned int cond,
snd_pcm_hw_param_t var,

85
sound/core/pcm_lib.c
View File

@ -1015,6 +1015,60 @@ int snd_interval_list(struct snd_interval *i, unsigned int count,
EXPORT_SYMBOL(snd_interval_list);
/**
* snd_interval_ranges - refine the interval value from the list of ranges
* @i: the interval value to refine
* @count: the number of elements in the list of ranges
* @ranges: the ranges list
* @mask: the bit-mask to evaluate
*
* Refines the interval value from the list of ranges.
* When mask is non-zero, only the elements corresponding to bit 1 are
* evaluated.
*
* Return: Positive if the value is changed, zero if it's not changed, or a
* negative error code.
*/
int snd_interval_ranges(struct snd_interval *i, unsigned int count,
const struct snd_interval *ranges, unsigned int mask)
{
unsigned int k;
struct snd_interval range_union;
struct snd_interval range;
if (!count) {
snd_interval_none(i);
return -EINVAL;
}
snd_interval_any(&range_union);
range_union.min = UINT_MAX;
range_union.max = 0;
for (k = 0; k < count; k++) {
if (mask && !(mask & (1 << k)))
continue;
snd_interval_copy(&range, &ranges[k]);
if (snd_interval_refine(&range, i) < 0)
continue;
if (snd_interval_empty(&range))
continue;
if (range.min < range_union.min) {
range_union.min = range.min;
range_union.openmin = 1;
}
if (range.min == range_union.min && !range.openmin)
range_union.openmin = 0;
if (range.max > range_union.max) {
range_union.max = range.max;
range_union.openmax = 1;
}
if (range.max == range_union.max && !range.openmax)
range_union.openmax = 0;
}
return snd_interval_refine(i, &range_union);
}
EXPORT_SYMBOL(snd_interval_ranges);
static int snd_interval_step(struct snd_interval *i, unsigned int step)
{
unsigned int n;
@ -1221,6 +1275,37 @@ int snd_pcm_hw_constraint_list(struct snd_pcm_runtime *runtime,
EXPORT_SYMBOL(snd_pcm_hw_constraint_list);
static int snd_pcm_hw_rule_ranges(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_pcm_hw_constraint_ranges *r = rule->private;
return snd_interval_ranges(hw_param_interval(params, rule->var),
r->count, r->ranges, r->mask);
}
/**
* snd_pcm_hw_constraint_ranges - apply list of range constraints to a parameter
* @runtime: PCM runtime instance
* @cond: condition bits
* @var: hw_params variable to apply the list of range constraints
* @r: ranges
*
* Apply the list of range constraints to an interval parameter.
*
* Return: Zero if successful, or a negative error code on failure.
*/
int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime,
unsigned int cond,
snd_pcm_hw_param_t var,
const struct snd_pcm_hw_constraint_ranges *r)
{
return snd_pcm_hw_rule_add(runtime, cond, var,
snd_pcm_hw_rule_ranges, (void *)r,
var, -1);
}
EXPORT_SYMBOL(snd_pcm_hw_constraint_ranges);
static int snd_pcm_hw_rule_ratnums(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{

932
sound/soc/codecs/pcm512x.c
View File

File diff suppressed because it is too large Load Diff

109
sound/soc/codecs/pcm512x.h
View File

@ -37,6 +37,10 @@
#define PCM512x_DSP_GPIO_INPUT (PCM512x_PAGE_BASE(0) + 10)
#define PCM512x_MASTER_MODE (PCM512x_PAGE_BASE(0) + 12)
#define PCM512x_PLL_REF (PCM512x_PAGE_BASE(0) + 13)
#define PCM512x_DAC_REF (PCM512x_PAGE_BASE(0) + 14)
#define PCM512x_GPIO_DACIN (PCM512x_PAGE_BASE(0) + 16)
#define PCM512x_GPIO_PLLIN (PCM512x_PAGE_BASE(0) + 18)
#define PCM512x_SYNCHRONIZE (PCM512x_PAGE_BASE(0) + 19)
#define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_BASE(0) + 20)
#define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_BASE(0) + 21)
#define PCM512x_PLL_COEFF_2 (PCM512x_PAGE_BASE(0) + 22)
@ -77,6 +81,7 @@
#define PCM512x_RATE_DET_2 (PCM512x_PAGE_BASE(0) + 92)
#define PCM512x_RATE_DET_3 (PCM512x_PAGE_BASE(0) + 93)
#define PCM512x_RATE_DET_4 (PCM512x_PAGE_BASE(0) + 94)
#define PCM512x_CLOCK_STATUS (PCM512x_PAGE_BASE(0) + 95)
#define PCM512x_ANALOG_MUTE_DET (PCM512x_PAGE_BASE(0) + 108)
#define PCM512x_GPIN (PCM512x_PAGE_BASE(0) + 119)
#define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAGE_BASE(0) + 120)
@ -91,7 +96,10 @@
#define PCM512x_CRAM_CTRL (PCM512x_PAGE_BASE(44) + 1)
#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(44) + 1)
#define PCM512x_FLEX_A (PCM512x_PAGE_BASE(253) + 63)
#define PCM512x_FLEX_B (PCM512x_PAGE_BASE(253) + 64)
#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(253) + 64)
/* Page 0, Register 1 - reset */
#define PCM512x_RSTR (1 << 0)
@ -108,8 +116,8 @@
#define PCM512x_RQML_SHIFT 4
/* Page 0, Register 4 - PLL */
#define PCM512x_PLCE (1 << 0)
#define PCM512x_RLCE_SHIFT 0
#define PCM512x_PLLE (1 << 0)
#define PCM512x_PLLE_SHIFT 0
#define PCM512x_PLCK (1 << 4)
#define PCM512x_PLCK_SHIFT 4
@ -119,8 +127,66 @@
#define PCM512x_DEMP (1 << 4)
#define PCM512x_DEMP_SHIFT 4
/* Page 0, Register 8 - GPIO output enable */
#define PCM512x_G1OE (1 << 0)
#define PCM512x_G2OE (1 << 1)
#define PCM512x_G3OE (1 << 2)
#define PCM512x_G4OE (1 << 3)
#define PCM512x_G5OE (1 << 4)
#define PCM512x_G6OE (1 << 5)
/* Page 0, Register 9 - BCK, LRCLK configuration */
#define PCM512x_LRKO (1 << 0)
#define PCM512x_LRKO_SHIFT 0
#define PCM512x_BCKO (1 << 4)
#define PCM512x_BCKO_SHIFT 4
#define PCM512x_BCKP (1 << 5)
#define PCM512x_BCKP_SHIFT 5
/* Page 0, Register 12 - Master mode BCK, LRCLK reset */
#define PCM512x_RLRK (1 << 0)
#define PCM512x_RLRK_SHIFT 0
#define PCM512x_RBCK (1 << 1)
#define PCM512x_RBCK_SHIFT 1
/* Page 0, Register 13 - PLL reference */
#define PCM512x_SREF (1 << 4)
#define PCM512x_SREF (7 << 4)
#define PCM512x_SREF_SHIFT 4
#define PCM512x_SREF_SCK (0 << 4)
#define PCM512x_SREF_BCK (1 << 4)
#define PCM512x_SREF_GPIO (3 << 4)
/* Page 0, Register 14 - DAC reference */
#define PCM512x_SDAC (7 << 4)
#define PCM512x_SDAC_SHIFT 4
#define PCM512x_SDAC_MCK (0 << 4)
#define PCM512x_SDAC_PLL (1 << 4)
#define PCM512x_SDAC_SCK (3 << 4)
#define PCM512x_SDAC_BCK (4 << 4)
#define PCM512x_SDAC_GPIO (5 << 4)
/* Page 0, Register 16, 18 - GPIO source for DAC, PLL */
#define PCM512x_GREF (7 << 0)
#define PCM512x_GREF_SHIFT 0
#define PCM512x_GREF_GPIO1 (0 << 0)
#define PCM512x_GREF_GPIO2 (1 << 0)
#define PCM512x_GREF_GPIO3 (2 << 0)
#define PCM512x_GREF_GPIO4 (3 << 0)
#define PCM512x_GREF_GPIO5 (4 << 0)
#define PCM512x_GREF_GPIO6 (5 << 0)
/* Page 0, Register 19 - synchronize */
#define PCM512x_RQSY (1 << 0)
#define PCM512x_RQSY_RESUME (0 << 0)
#define PCM512x_RQSY_HALT (1 << 0)
/* Page 0, Register 34 - fs speed mode */
#define PCM512x_FSSP (3 << 0)
#define PCM512x_FSSP_SHIFT 0
#define PCM512x_FSSP_48KHZ (0 << 0)
#define PCM512x_FSSP_96KHZ (1 << 0)
#define PCM512x_FSSP_192KHZ (2 << 0)
#define PCM512x_FSSP_384KHZ (3 << 0)
/* Page 0, Register 37 - Error detection */
#define PCM512x_IPLK (1 << 0)
@ -131,6 +197,20 @@
#define PCM512x_IDBK (1 << 5)
#define PCM512x_IDFS (1 << 6)
/* Page 0, Register 40 - I2S configuration */
#define PCM512x_ALEN (3 << 0)
#define PCM512x_ALEN_SHIFT 0
#define PCM512x_ALEN_16 (0 << 0)
#define PCM512x_ALEN_20 (1 << 0)
#define PCM512x_ALEN_24 (2 << 0)
#define PCM512x_ALEN_32 (3 << 0)
#define PCM512x_AFMT (3 << 4)
#define PCM512x_AFMT_SHIFT 4
#define PCM512x_AFMT_I2S (0 << 4)
#define PCM512x_AFMT_DSP (1 << 4)
#define PCM512x_AFMT_RTJ (2 << 4)
#define PCM512x_AFMT_LTJ (3 << 4)
/* Page 0, Register 42 - DAC routing */
#define PCM512x_AUPR_SHIFT 0
#define PCM512x_AUPL_SHIFT 4
@ -152,7 +232,26 @@
/* Page 0, Register 65 - Digital mute enables */
#define PCM512x_ACTL_SHIFT 2
#define PCM512x_AMLE_SHIFT 1
#define PCM512x_AMLR_SHIFT 0
#define PCM512x_AMRE_SHIFT 0
/* Page 0, Register 80-85, GPIO output selection */
#define PCM512x_GxSL (31 << 0)
#define PCM512x_GxSL_SHIFT 0
#define PCM512x_GxSL_OFF (0 << 0)
#define PCM512x_GxSL_DSP (1 << 0)
#define PCM512x_GxSL_REG (2 << 0)
#define PCM512x_GxSL_AMUTB (3 << 0)
#define PCM512x_GxSL_AMUTL (4 << 0)
#define PCM512x_GxSL_AMUTR (5 << 0)
#define PCM512x_GxSL_CLKI (6 << 0)
#define PCM512x_GxSL_SDOUT (7 << 0)
#define PCM512x_GxSL_ANMUL (8 << 0)
#define PCM512x_GxSL_ANMUR (9 << 0)
#define PCM512x_GxSL_PLLLK (10 << 0)
#define PCM512x_GxSL_CPCLK (11 << 0)
#define PCM512x_GxSL_UV0_7 (14 << 0)
#define PCM512x_GxSL_UV0_3 (15 << 0)
#define PCM512x_GxSL_PLLCK (16 << 0)
/* Page 1, Register 2 - analog volume control */
#define PCM512x_RAGN_SHIFT 0