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staging:rtl8192u: Clean up of spacing - Style

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Multiple blank line, which cause an issue with checkpath, have been
removed and the spacing of definitions have been aligned to look
cleaner.

These are coding style changes which should have no impact on
runtime code execution.

Signed-off-by: John Whitmore <johnfwhitmore@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
John Whitmore 2018-08-03 01:02:11 +01:00 committed by Greg Kroah-Hartman
parent 1bb6d9b950
commit 0f79619d70
1 changed files with 58 additions and 65 deletions
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123
drivers/staging/rtl8192u/r8192U_dm.h
View File

@ -21,48 +21,46 @@
#ifndef __R8192UDM_H__
#define __R8192UDM_H__
/*--------------------------Define Parameters-------------------------------*/
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
#define DM_DIG_HIGH_PWR_THRESH_LOW 70
#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
#define DM_DIG_HIGH_PWR_THRESH_LOW 70
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_DIG_BACKOFF 12
#define DM_DIG_MAX 0x36
#define DM_DIG_MIN 0x1c
#define DM_DIG_MIN_NETCORE 0x12
#define DM_DIG_BACKOFF 12
#define DM_DIG_MAX 0x36
#define DM_DIG_MIN 0x1c
#define DM_DIG_MIN_NETCORE 0x12
#define RX_PATH_SELECTION_SS_TH_LOW 30
#define RX_PATH_SELECTION_DIFF_TH 18
#define RX_PATH_SELECTION_SS_TH_LOW 30
#define RX_PATH_SELECTION_DIFF_TH 18
#define RATE_ADAPTIVE_TH_HIGH 50
#define RATE_ADAPTIVE_TH_LOW_20M 30
#define RATE_ADAPTIVE_TH_LOW_40M 10
#define VERY_LOW_RSSI 15
#define CTS_TO_SELF_TH_VAL 30
#define RATE_ADAPTIVE_TH_HIGH 50
#define RATE_ADAPTIVE_TH_LOW_20M 30
#define RATE_ADAPTIVE_TH_LOW_40M 10
#define VERY_LOW_RSSI 15
#define CTS_TO_SELF_TH_VAL 30
/* defined by vivi, for tx power track */
#define E_FOR_TX_POWER_TRACK 300
#define E_FOR_TX_POWER_TRACK 300
/* Dynamic Tx Power Control Threshold */
#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
/* added by amy for atheros AP */
#define TX_POWER_ATHEROAP_THRESH_HIGH 78
#define TX_POWER_ATHEROAP_THRESH_LOW 72
#define TX_POWER_ATHEROAP_THRESH_LOW 72
/* defined by vivi, for showing on UI */
#define CURRENT_TX_RATE_REG 0x1b8
#define INITIAL_TX_RATE_REG 0x1b9
#define TX_RETRY_COUNT_REG 0x1ac
#define REG_C38_TH 20
#define CURRENT_TX_RATE_REG 0x1b8
#define INITIAL_TX_RATE_REG 0x1b9
#define TX_RETRY_COUNT_REG 0x1ac
#define REG_C38_TH 20
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
enum dig_algorithm {
@ -78,49 +76,49 @@ enum dynamic_init_gain_state {
enum dig_connect {
DIG_DISCONNECT = 0,
DIG_CONNECT = 1,
DIG_CONNECT = 1,
};
enum dig_pkt_detection_threshold {
DIG_PD_AT_LOW_POWER = 0,
DIG_PD_AT_LOW_POWER = 0,
DIG_PD_AT_NORMAL_POWER = 1,
DIG_PD_AT_HIGH_POWER = 2,
DIG_PD_AT_HIGH_POWER = 2,
};
enum dig_cck_cs_ratio_state {
DIG_CS_RATIO_LOWER = 0,
DIG_CS_RATIO_LOWER = 0,
DIG_CS_RATIO_HIGHER = 1,
};
/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
struct dig {
u8 dig_enable_flag;
enum dig_algorithm dig_algorithm;
u8 dig_algorithm_switch;
u8 dig_enable_flag;
enum dig_algorithm dig_algorithm;
u8 dig_algorithm_switch;
long rssi_low_thresh;
long rssi_high_thresh;
long rssi_low_thresh;
long rssi_high_thresh;
long rssi_high_power_lowthresh;
long rssi_high_power_highthresh;
long rssi_high_power_lowthresh;
long rssi_high_power_highthresh;
enum dynamic_init_gain_state dig_state;
enum dynamic_init_gain_state dig_highpwr_state;
enum dig_connect cur_connect_state;
enum dig_connect pre_connect_state;
enum dynamic_init_gain_state dig_state;
enum dynamic_init_gain_state dig_highpwr_state;
enum dig_connect cur_connect_state;
enum dig_connect pre_connect_state;
enum dig_pkt_detection_threshold curpd_thstate;
enum dig_pkt_detection_threshold prepd_thstate;
enum dig_cck_cs_ratio_state curcs_ratio_state;
enum dig_cck_cs_ratio_state precs_ratio_state;
enum dig_pkt_detection_threshold curpd_thstate;
enum dig_pkt_detection_threshold prepd_thstate;
enum dig_cck_cs_ratio_state curcs_ratio_state;
enum dig_cck_cs_ratio_state precs_ratio_state;
u32 pre_ig_value;
u32 cur_ig_value;
u32 pre_ig_value;
u32 cur_ig_value;
u8 backoff_val;
u8 rx_gain_range_min;
u8 backoff_val;
u8 rx_gain_range_min;
long rssi_val;
long rssi_val;
};
enum cck_rx_path_method {
@ -129,36 +127,33 @@ enum cck_rx_path_method {
};
struct dynamic_rx_path_sel {
enum cck_rx_path_method cck_method;
u8 cck_rx_path;
enum cck_rx_path_method cck_method;
u8 cck_rx_path;
u8 disabled_rf;
u8 disabled_rf;
u8 rf_rssi[4];
u8 rf_enable_rssi_th[4];
long cck_pwdb_sta[4];
u8 rf_rssi[4];
u8 rf_enable_rssi_th[4];
long cck_pwdb_sta[4];
};
struct tx_config_cmd {
u32 cmd_op; /* Command packet type. */
u32 cmd_length; /* Command packet length. */
u32 cmd_value;
u32 cmd_op; /* Command packet type. */
u32 cmd_length; /* Command packet length. */
u32 cmd_value;
};
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
extern struct dig dm_digtable;
extern u8 dm_shadow[16][256];
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
void init_hal_dm(struct net_device *dev);
void deinit_hal_dm(struct net_device *dev);
@ -178,8 +173,6 @@ void dm_shadow_init(struct net_device *dev);
void dm_initialize_txpower_tracking(struct net_device *dev);
/*--------------------------Exported Function prototype---------------------*/
#endif /*__R8192UDM_H__ */
/* End of r8192U_dm.h */