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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC]: Missing #include <linux/mm.h> in drivers/sbus/char/flash.c [SPARC32]: Build fix. [SPARC64]: Add missing NCS and SVC hypervisor interfaces.
This commit is contained in:
Linus Torvalds
commit
0e9871df23
@ -124,10 +124,10 @@ unsigned long __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new)
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unsigned long flags;
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u32 prev;
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spin_lock_irqsave(ATOMIC_HASH(addr), flags);
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spin_lock_irqsave(ATOMIC_HASH(ptr), flags);
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if ((prev = *ptr) == old)
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*ptr = new;
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spin_unlock_irqrestore(ATOMIC_HASH(addr), flags);
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spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags);
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return (unsigned long)prev;
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}
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@ -2498,3 +2498,75 @@ sun4v_vintr_set_target:
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retl
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nop
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.size sun4v_vintr_set_target, .-sun4v_vintr_set_target
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/* %o0: NCS sub-function
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* %o1: sub-function arg real-address
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* %o2: sub-function arg size
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*
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* returns %o0: status
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*/
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.globl sun4v_ncs_request
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.type sun4v_ncs_request,#function
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sun4v_ncs_request:
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mov HV_FAST_NCS_REQUEST, %o5
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ta HV_FAST_TRAP
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retl
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nop
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.size sun4v_ncs_request, .-sun4v_ncs_request
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.globl sun4v_scv_send
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.type sun4v_scv_send,#function
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sun4v_scv_send:
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save %sp, -192, %sp
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mov %i0, %o0
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mov %i1, %o1
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mov %i2, %o2
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mov HV_FAST_SVC_SEND, %o5
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ta HV_FAST_TRAP
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stx %o1, [%i3]
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ret
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restore
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.size sun4v_scv_send, .-sun4v_scv_send
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.globl sun4v_scv_recv
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.type sun4v_scv_recv,#function
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sun4v_scv_recv:
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save %sp, -192, %sp
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mov %i0, %o0
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mov %i1, %o1
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mov %i2, %o2
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mov HV_FAST_SVC_RECV, %o5
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ta HV_FAST_TRAP
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stx %o1, [%i3]
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ret
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restore
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.size sun4v_scv_recv, .-sun4v_scv_recv
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.globl sun4v_scv_getstatus
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.type sun4v_scv_getstatus,#function
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sun4v_scv_getstatus:
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mov HV_FAST_SVC_GETSTATUS, %o5
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mov %o1, %o4
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ta HV_FAST_TRAP
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stx %o1, [%o4]
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retl
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nop
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.size sun4v_scv_getstatus, .-sun4v_scv_getstatus
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.globl sun4v_scv_setstatus
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.type sun4v_scv_setstatus,#function
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sun4v_scv_setstatus:
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mov HV_FAST_SVC_SETSTATUS, %o5
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ta HV_FAST_TRAP
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retl
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nop
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.size sun4v_scv_setstatus, .-sun4v_scv_setstatus
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.globl sun4v_scv_clrstatus
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.type sun4v_scv_clrstatus,#function
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sun4v_scv_clrstatus:
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mov HV_FAST_SVC_CLRSTATUS, %o5
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ta HV_FAST_TRAP
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retl
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nop
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.size sun4v_scv_clrstatus, .-sun4v_scv_clrstatus
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@ -14,6 +14,7 @@
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#include <linux/init.h>
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#include <linux/smp_lock.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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@ -1097,6 +1097,80 @@ extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
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*/
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#define HV_FAST_MACH_GET_SOFT_STATE 0x71
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/* svc_send()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_SVC_SEND
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* ARG0: service ID
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* ARG1: buffer real address
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* ARG2: buffer size
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* RET0: STATUS
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* RET1: sent_bytes
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*
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* Be careful, all output registers are clobbered by this operation,
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* so for example it is not possible to save away a value in %o4
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* across the trap.
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*/
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#define HV_FAST_SVC_SEND 0x80
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/* svc_recv()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_SVC_RECV
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* ARG0: service ID
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* ARG1: buffer real address
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* ARG2: buffer size
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* RET0: STATUS
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* RET1: recv_bytes
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*
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* Be careful, all output registers are clobbered by this operation,
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* so for example it is not possible to save away a value in %o4
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* across the trap.
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*/
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#define HV_FAST_SVC_RECV 0x81
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/* svc_getstatus()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_SVC_GETSTATUS
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* ARG0: service ID
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* RET0: STATUS
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* RET1: status bits
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*/
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#define HV_FAST_SVC_GETSTATUS 0x82
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/* svc_setstatus()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_SVC_SETSTATUS
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* ARG0: service ID
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* ARG1: bits to set
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* RET0: STATUS
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*/
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#define HV_FAST_SVC_SETSTATUS 0x83
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/* svc_clrstatus()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_SVC_CLRSTATUS
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* ARG0: service ID
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* ARG1: bits to clear
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* RET0: STATUS
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*/
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#define HV_FAST_SVC_CLRSTATUS 0x84
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#ifndef __ASSEMBLY__
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extern unsigned long sun4v_svc_send(unsigned long svc_id,
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unsigned long buffer,
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unsigned long buffer_size,
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unsigned long *sent_bytes);
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extern unsigned long sun4v_svc_recv(unsigned long svc_id,
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unsigned long buffer,
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unsigned long buffer_size,
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unsigned long *recv_bytes);
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extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
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unsigned long *status_bits);
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extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
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unsigned long status_bits);
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extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
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unsigned long status_bits);
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#endif
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/* Trap trace services.
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*
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* The hypervisor provides a trap tracing capability for privileged
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@ -2724,6 +2798,100 @@ struct hv_mmu_statistics {
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*/
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#define HV_FAST_MMUSTAT_INFO 0x103
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/* NCS crypto services */
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/* ncs_request() sub-function numbers */
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#define HV_NCS_QCONF 0x01
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#define HV_NCS_QTAIL_UPDATE 0x02
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#ifndef __ASSEMBLY__
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struct hv_ncs_queue_entry {
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/* MAU Control Register */
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unsigned long mau_control;
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#define MAU_CONTROL_INV_PARITY 0x0000000000002000
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#define MAU_CONTROL_STRAND 0x0000000000001800
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#define MAU_CONTROL_BUSY 0x0000000000000400
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#define MAU_CONTROL_INT 0x0000000000000200
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#define MAU_CONTROL_OP 0x00000000000001c0
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#define MAU_CONTROL_OP_SHIFT 6
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#define MAU_OP_LOAD_MA_MEMORY 0x0
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#define MAU_OP_STORE_MA_MEMORY 0x1
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#define MAU_OP_MODULAR_MULT 0x2
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#define MAU_OP_MODULAR_REDUCE 0x3
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#define MAU_OP_MODULAR_EXP_LOOP 0x4
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#define MAU_CONTROL_LEN 0x000000000000003f
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#define MAU_CONTROL_LEN_SHIFT 0
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/* Real address of bytes to load or store bytes
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* into/out-of the MAU.
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*/
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unsigned long mau_mpa;
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/* Modular Arithmetic MA Offset Register. */
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unsigned long mau_ma;
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/* Modular Arithmetic N Prime Register. */
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unsigned long mau_np;
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};
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struct hv_ncs_qconf_arg {
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unsigned long mid; /* MAU ID, 1 per core on Niagara */
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unsigned long base; /* Real address base of queue */
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unsigned long end; /* Real address end of queue */
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unsigned long num_ents; /* Number of entries in queue */
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};
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struct hv_ncs_qtail_update_arg {
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unsigned long mid; /* MAU ID, 1 per core on Niagara */
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unsigned long tail; /* New tail index to use */
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unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
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#define HV_NCS_SYNCFLAG_SYNC 0x00
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#define HV_NCS_SYNCFLAG_ASYNC 0x01
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};
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#endif
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/* ncs_request()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_REQUEST
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* ARG0: NCS sub-function
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* ARG1: sub-function argument real address
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* ARG2: size in bytes of sub-function argument
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* RET0: status
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*
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* The MAU chip of the Niagara processor is not directly accessible
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* to privileged code, instead it is programmed indirectly via this
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* hypervisor API.
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*
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* The interfaces defines a queue of MAU operations to perform.
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* Privileged code registers a queue with the hypervisor by invoking
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* this HVAPI with the HV_NCS_QCONF sub-function, which defines the
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* base, end, and number of entries of the queue. Each queue entry
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* contains a MAU register struct block.
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*
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* The privileged code then proceeds to add entries to the queue and
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* then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
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* synchronous operations are supported by the current hypervisor,
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* HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
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* completion and return HV_EOK, or return an error code.
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*
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* The real address of the sub-function argument must be aligned on at
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* least an 8-byte boundary.
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*
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* The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
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* offset, into the queue and must be less than or equal the 'num_ents'
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* argument given in the HV_NCS_QCONF call.
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*/
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#define HV_FAST_NCS_REQUEST 0x110
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#ifndef __ASSEMBLY__
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extern unsigned long sun4v_ncs_request(unsigned long request,
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unsigned long arg_ra,
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unsigned long arg_size);
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#endif
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#define HV_FAST_FIRE_GET_PERFREG 0x120
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#define HV_FAST_FIRE_SET_PERFREG 0x121
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/* Function numbers for HV_CORE_TRAP. */
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#define HV_CORE_SET_VER 0x00
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#define HV_CORE_PUTCHAR 0x01
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