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Merge branch 'devel-omap5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/newsoc

Browse Source 
From Tony Lindgren <tony@atomide.com>:

This branch contains minimal support for omap5 to boot to a
console without clock framework support. This branch depends
on omap-cleanup-part2-for-v3.6.

* 'devel-omap5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: Kconfig update to support additional GPIOs in OMAP5
  ARM: OMAP5: Add the build support
  arm/dts: OMAP5: Add omap5 dts files
  ARM: OMAP5: board-generic: Add device tree support
  ARM: omap2+: board-generic: clean up the irq data from board file
  ARM: OMAP5: Add SMP support
  ARM: OMAP5: Add the WakeupGen IP updates
  ARM: OMAP5: l3: Add l3 error handler support for omap5
  ARM: OMAP5: gpmc: Update gpmc_init()
  ARM: OMAP5: timer: Add clocksource, clockevent support
  ARM: OMAP5: Add minimal support for OMAP5430 SOC
  ARM: OMAP5: id: Add cpu id for ES versions
  ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme
  ARM: OMAP2+: Move stubbed secure_sram_reserve function to a common.c and call it __weak

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-07-10 17:43:22 +02:00
commit 0e3585113f
41 changed files with 772 additions and 97 deletions
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3
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@ -47,3 +47,6 @@ Boards:
- AM335X EVM : Software Developement Board for AM335x
compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"

1
arch/arm/Kconfig
View File

@ -1595,6 +1595,7 @@ config ARCH_NR_GPIO
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
default 512 if SOC_OMAP5
default 0
help
Maximum number of GPIOs in the system.

20
arch/arm/boot/dts/omap5-evm.dts Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap5.dtsi"
/ {
model = "TI OMAP5 EVM board";
compatible = "ti,omap5-evm", "ti,omap5";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};

184
arch/arm/boot/dts/omap5.dtsi Normal file
View File

@ -0,0 +1,184 @@
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Based on "omap4.dtsi"
*/
/*
* Carveout for multimedia usecases
* It should be the last 48MB of the first 512MB memory part
* In theory, it should not even exist. That zone should be reserved
* dynamically during the .reserve callback.
*/
/memreserve/ 0x9d000000 0x03000000;
/include/ "skeleton.dtsi"
/ {
compatible = "ti,omap5";
interrupt-parent = <&gic>;
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
};
cpus {
cpu@0 {
compatible = "arm,cortex-a15";
};
cpu@1 {
compatible = "arm,cortex-a15";
};
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap5-mpu";
ti,hwmods = "mpu";
};
};
/*
* XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48211000 0x1000>,
<0x48212000 0x1000>;
};
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio7: gpio@48051000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio7";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio8: gpio@48053000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio8";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
uart5: serial@48066000 {
compatible = "ti,omap5-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
};
uart6: serial@48068000 {
compatible = "ti,omap6-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
};
};
};

1
arch/arm/configs/omap2plus_defconfig
View File

@ -236,3 +236,4 @@ CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_SOC_OMAP5=y

8
arch/arm/mach-omap2/Kconfig
View File

@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
select REGULATOR
select PM_RUNTIME
select VFP
select NEON if ARCH_OMAP3 || ARCH_OMAP4
select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
select SERIAL_OMAP
select SERIAL_OMAP_CONSOLE
select I2C
@ -61,6 +61,12 @@ config ARCH_OMAP4
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARM_CPU_SUSPEND if PM
config SOC_OMAP5
bool "TI OMAP5"
select CPU_V7
select ARM_GIC
select HAVE_SMP
comment "OMAP Core Type"
depends on ARCH_OMAP2

24
arch/arm/mach-omap2/Makefile
View File

@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
@ -29,8 +30,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
omap-4-5-common = omap4-common.o omap-wakeupgen.o \
sleep44xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@ -70,6 +73,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
@ -85,14 +89,16 @@ endif
endif
# PRCM
omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
prcm_mpu44xx.o prminst44xx.o \
vc44xx_data.o vp44xx_data.o
obj-y += prm_common.o
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@ -104,6 +110,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
@ -121,6 +128,8 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
@ -139,6 +148,8 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@ -157,6 +168,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
@ -184,6 +197,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
# L3 interconnect
obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
obj-$(CONFIG_SOC_OMAP5) += omap_l3_noc.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o

42
arch/arm/mach-omap2/board-generic.c
View File

@ -25,23 +25,12 @@
#include "common-board-devices.h"
#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
#define omap_intc_of_init NULL
#define intc_of_init NULL
#endif
#ifndef CONFIG_ARCH_OMAP4
#define gic_of_init NULL
#endif
static struct of_device_id irq_match[] __initdata = {
{ .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{ }
};
static void __init omap_init_irq(void)
{
of_irq_init(irq_match);
}
static struct of_device_id omap_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
{ .compatible = "ti,omap-infra", },
@ -65,7 +54,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap_init_irq,
.init_irq = omap_intc_of_init,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
@ -84,7 +73,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_irq = omap_init_irq,
.init_irq = omap_intc_of_init,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
@ -103,7 +92,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap_init_irq,
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap3_timer,
@ -122,7 +111,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = am33xx_map_io,
.init_early = am33xx_init_early,
.init_irq = omap_init_irq,
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap3_am33xx_timer,
@ -140,7 +129,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = omap_init_irq,
.init_irq = omap_gic_of_init,
.handle_irq = gic_handle_irq,
.init_machine = omap_generic_init,
.init_late = omap4430_init_late,
@ -149,3 +138,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.restart = omap_prcm_restart,
MACHINE_END
#endif
#ifdef CONFIG_SOC_OMAP5
static const char *omap5_boards_compat[] __initdata = {
"ti,omap5",
NULL,
};
DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap5_map_io,
.init_early = omap5_init_early,
.init_irq = omap_gic_of_init,
.handle_irq = gic_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap5_timer,
.dt_compat = omap5_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
#endif

24
arch/arm/mach-omap2/common.c
View File

@ -178,3 +178,27 @@ void __init omap4_map_io(void)
}
#endif
#if defined(CONFIG_SOC_OMAP5)
static struct omap_globals omap5_globals = {
.class = OMAP54XX_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
.ctrl = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
.ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE),
.prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
.cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
.prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
};
void __init omap2_set_globals_5xxx(void)
{
omap2_set_globals_tap(&omap5_globals);
omap2_set_globals_control(&omap5_globals);
omap2_set_globals_prcm(&omap5_globals);
}
void __init omap5_map_io(void)
{
omap5_map_common_io();
}
#endif

19
arch/arm/mach-omap2/common.h
View File

@ -115,6 +115,14 @@ static inline int omap_mux_late_init(void)
}
#endif
#ifdef CONFIG_SOC_OMAP5
extern void omap5_map_common_io(void);
#else
static inline void omap5_map_common_io(void)
{
}
#endif
extern void omap2_init_common_infrastructure(void);
extern struct sys_timer omap2_timer;
@ -122,6 +130,7 @@ extern struct sys_timer omap3_timer;
extern struct sys_timer omap3_secure_timer;
extern struct sys_timer omap3_am33xx_timer;
extern struct sys_timer omap4_timer;
extern struct sys_timer omap5_timer;
void omap2420_init_early(void);
void omap2430_init_early(void);
@ -134,6 +143,7 @@ void am35xx_init_early(void);
void ti81xx_init_early(void);
void am33xx_init_early(void);
void omap4430_init_early(void);
void omap5_init_early(void);
void omap3_init_late(void); /* Do not use this one */
void omap4430_init_late(void);
void omap2420_init_late(void);
@ -169,6 +179,7 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
void omap2_set_globals_5xxx(void);
void omap2_set_globals_ti81xx(void);
void omap2_set_globals_am33xx(void);
@ -188,6 +199,7 @@ void omap243x_map_io(void);
void omap3_map_io(void);
void am33xx_map_io(void);
void omap4_map_io(void);
void omap5_map_io(void);
void ti81xx_map_io(void);
void omap_barriers_init(void);
@ -227,6 +239,8 @@ void omap3_intc_prepare_idle(void);
void omap3_intc_resume_idle(void);
void omap2_intc_handle_irq(struct pt_regs *regs);
void omap3_intc_handle_irq(struct pt_regs *regs);
void omap_intc_of_init(void);
void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *omap4_get_l2cache_base(void);
@ -234,10 +248,10 @@ extern void __iomem *omap4_get_l2cache_base(void);
struct device_node;
#ifdef CONFIG_OF
int __init omap_intc_of_init(struct device_node *node,
int __init intc_of_init(struct device_node *node,
struct device_node *parent);
#else
int __init omap_intc_of_init(struct device_node *node,
int __init intc_of_init(struct device_node *node,
struct device_node *parent)
{
return 0;
@ -264,6 +278,7 @@ extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);
extern void omap5_secondary_startup(void);
#endif
#if defined(CONFIG_SMP) && defined(CONFIG_PM)

4
arch/arm/mach-omap2/control.h
View File

@ -253,6 +253,10 @@
/* TI81XX CONTROL_DEVCONF register offsets */
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
/* OMAP54XX CONTROL STATUS register */
#define OMAP5XXX_CONTROL_STATUS 0x134
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.

2
arch/arm/mach-omap2/devices.c
View File

@ -84,7 +84,7 @@ static int __init omap4_l3_init(void)
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!(cpu_is_omap44xx()))
if (!cpu_is_omap44xx() && !soc_is_omap54xx())
return -ENODEV;
for (i = 0; i < L3_MODULES; i++) {

3
arch/arm/mach-omap2/gpmc.c
View File

@ -727,7 +727,8 @@ static int __init gpmc_init(void)
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
gpmc_irq = INT_34XX_GPMC_IRQ;
} else if (cpu_is_omap44xx()) {
} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
/* Base address and irq number are same for OMAP4/5 */
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
gpmc_irq = OMAP44XX_IRQ_GPMC;

42
arch/arm/mach-omap2/id.c
View File

@ -50,6 +50,11 @@ int omap_type(void)
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
} else if (soc_is_omap54xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
val &= OMAP5_DEVICETYPE_MASK;
val >>= 6;
goto out;
} else {
pr_err("Cannot detect omap type!\n");
goto out;
@ -100,7 +105,7 @@ static u16 tap_prod_id;
void omap_get_die_id(struct omap_die_id *odi)
{
if (cpu_is_omap44xx()) {
if (cpu_is_omap44xx() || soc_is_omap54xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@ -513,6 +518,41 @@ void __init omap4xxx_check_revision(void)
((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}
void __init omap5xxx_check_revision(void)
{
u32 idcode;
u16 hawkeye;
u8 rev;
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
switch (hawkeye) {
case 0xb942:
switch (rev) {
case 0:
default:
omap_revision = OMAP5430_REV_ES1_0;
}
break;
case 0xb998:
switch (rev) {
case 0:
default:
omap_revision = OMAP5432_REV_ES1_0;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP5430_REV_ES1_0;
}
pr_info("OMAP%04x ES%d.0\n",
omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
}
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets

8
arch/arm/mach-omap2/include/mach/debug-macro.S
View File

@ -60,12 +60,12 @@ omap_uart_lsr: .word 0
beq 23f @ configure OMAP2UART3
cmp \rp, #OMAP3UART3 @ only on 34xx
beq 33f @ configure OMAP3UART3
cmp \rp, #OMAP4UART3 @ only on 44xx
beq 43f @ configure OMAP4UART3
cmp \rp, #OMAP4UART3 @ only on 44xx/54xx
beq 43f @ configure OMAP4/5UART3
cmp \rp, #OMAP3UART4 @ only on 36xx
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
cmp \rp, #OMAP4UART4 @ only on 44xx/54xx
beq 44f @ configure OMAP4/5UART4
cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different

7
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
View File

@ -11,15 +11,20 @@
#ifndef OMAP_ARCH_WAKEUPGEN_H
#define OMAP_ARCH_WAKEUPGEN_H
/* OMAP4 and OMAP5 has same base address */
#define OMAP_WKUPGEN_BASE 0x48281000
#define OMAP_WKG_CONTROL_0 0x00
#define OMAP_WKG_ENB_A_0 0x10
#define OMAP_WKG_ENB_B_0 0x14
#define OMAP_WKG_ENB_C_0 0x18
#define OMAP_WKG_ENB_D_0 0x1c
#define OMAP_WKG_ENB_E_0 0x20
#define OMAP_WKG_ENB_A_1 0x410
#define OMAP_WKG_ENB_B_1 0x414
#define OMAP_WKG_ENB_C_1 0x418
#define OMAP_WKG_ENB_D_1 0x41c
#define OMAP_WKG_ENB_E_1 0x420
#define OMAP_AUX_CORE_BOOT_0 0x800
#define OMAP_AUX_CORE_BOOT_1 0x804
#define OMAP_PTMSYNCREQ_MASK 0xc00
@ -28,4 +33,6 @@
#define OMAP_TIMESTAMPCYCLEHI 0xc0c
extern int __init omap_wakeupgen_init(void);
extern void __iomem *omap_get_wakeupgen_base(void);
extern int omap_secure_apis_support(void);
#endif

44
arch/arm/mach-omap2/io.c
View File

@ -233,6 +233,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif
#ifdef CONFIG_SOC_OMAP5
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
.pfn = __phys_to_pfn(L3_54XX_PHYS),
.length = L3_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_54XX_VIRT,
.pfn = __phys_to_pfn(L4_54XX_PHYS),
.length = L4_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_WK_54XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
.length = L4_WK_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER_54XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
.length = L4_PER_54XX_SIZE,
.type = MT_DEVICE,
},
};
#endif
#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_common_io(void)
{
@ -278,6 +307,12 @@ void __init omap44xx_map_common_io(void)
}
#endif
#ifdef CONFIG_SOC_OMAP5
void __init omap5_map_common_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
}
#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
@ -513,6 +548,15 @@ void __init omap4430_init_late(void)
}
#endif
#ifdef CONFIG_SOC_OMAP5
void __init omap5_init_early(void)
{
omap2_set_globals_5xxx();
omap5xxx_check_revision();
omap_common_init_early();
}
#endif
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{

27
arch/arm/mach-omap2/iomap.h
View File

@ -1,6 +1,14 @@
/*
* IO mappings for OMAP2+
*
* IO definitions for TI OMAP processors and boards
*
* Copied from arch/arm/mach-sa1100/include/mach/io.h
* Copyright (C) 1997-1999 Russell King
*
* Copyright (C) 2009-2012 Texas Instruments
* Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@ -166,4 +174,23 @@
/* 0x49000000 --> 0xfb000000 */
#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_ABE_44XX_SIZE SZ_1M
/*
* ----------------------------------------------------------------------------
* Omap5 specific IO mapping
* ----------------------------------------------------------------------------
*/
#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */
#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
#define L3_54XX_SIZE SZ_1M
#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */
#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_54XX_SIZE SZ_4M
#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_WK_54XX_SIZE SZ_2M
#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_PER_54XX_SIZE SZ_4M

13
arch/arm/mach-omap2/irq.c
View File

@ -21,6 +21,7 @@
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <mach/hardware.h>
@ -258,7 +259,7 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
omap_intc_handle_irq(base_addr, regs);
}
int __init omap_intc_of_init(struct device_node *node,
int __init intc_of_init(struct device_node *node,
struct device_node *parent)
{
struct resource res;
@ -280,6 +281,16 @@ int __init omap_intc_of_init(struct device_node *node,
return 0;
}
static struct of_device_id irq_match[] __initdata = {
{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
{ }
};
void __init omap_intc_of_init(void)
{
of_irq_init(irq_match);
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

21
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -19,6 +19,27 @@
#include <linux/init.h>
__CPUINIT
/* Physical address needed since MMU not enabled yet on secondary core */
#define AUX_CORE_BOOT0_PA 0x48281800
/*
* OMAP5 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise.
* The primary core will update this flag using a hardware
+ * register AuxCoreBoot0.
*/
ENTRY(omap5_secondary_startup)
wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
ldr r0, [r2]
mov r0, r0, lsr #5
mrc p15, 0, r4, c0, c0, 5
and r4, r4, #0x0f
cmp r0, r4
bne wait
b secondary_startup
END(omap5_secondary_startup)
/*
* OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which

24
arch/arm/mach-omap2/omap-hotplug.c
View File

@ -17,8 +17,10 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <mach/omap-wakeupgen.h>
#include "common.h"
@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
*/
void __ref platform_cpu_die(unsigned int cpu)
{
unsigned int this_cpu;
unsigned int boot_cpu = 0;
void __iomem *base = omap_get_wakeupgen_base();
flush_cache_all();
dsb();
@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
/*
* we're ready for shutdown now, so do it
*/
if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
pr_err("Secure clear status failed\n");
if (omap_secure_apis_support()) {
if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
pr_err("Secure clear status failed\n");
} else {
__raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
}
for (;;) {
/*
* Enter into low power state
*/
omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
this_cpu = smp_processor_id();
if (omap_read_auxcoreboot0() == this_cpu) {
if (omap_secure_apis_support())
boot_cpu = omap_read_auxcoreboot0();
else
boot_cpu =
__raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
if (boot_cpu == smp_processor_id()) {
/*
* OK, proper wakeup, we're done
*/

50
arch/arm/mach-omap2/omap-smp.c
View File

@ -26,11 +26,19 @@
#include <mach/hardware.h>
#include <mach/omap-secure.h>
#include <mach/omap-wakeupgen.h>
#include <asm/cputype.h>
#include "iomap.h"
#include "common.h"
#include "clockdomain.h"
#define CPU_MASK 0xff0ffff0
#define CPU_CORTEX_A9 0x410FC090
#define CPU_CORTEX_A15 0x410FC0F0
#define OMAP5_CORE_COUNT 0x2
/* SCU base address */
static void __iomem *scu_base;
@ -73,6 +81,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static struct clockdomain *cpu1_clkdm;
static bool booted;
void __iomem *base = omap_get_wakeupgen_base();
/*
* Set synchronisation state between this boot processor
* and the secondary one
@ -85,7 +95,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the AuxCoreBoot1 register is updated with cpu state
* A barrier is added to ensure that write buffer is drained
*/
omap_modify_auxcoreboot0(0x200, 0xfffffdff);
if (omap_secure_apis_support())
omap_modify_auxcoreboot0(0x200, 0xfffffdff);
else
__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
flush_cache_all();
smp_wmb();
@ -124,13 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init wakeup_secondary(void)
{
void __iomem *base = omap_get_wakeupgen_base();
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
smp_wmb();
/*
@ -147,16 +167,21 @@ static void __init wakeup_secondary(void)
*/
void __init smp_init_cpus(void)
{
unsigned int i, ncores;
unsigned int i = 0, ncores = 1, cpu_id;
/*
* Currently we can't call ioremap here because
* SoC detection won't work until after init_early.
*/
scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
BUG_ON(!scu_base);
ncores = scu_get_core_count(scu_base);
/* Use ARM cpuid check here, as SoC detection will not work so early */
cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
if (cpu_id == CPU_CORTEX_A9) {
/*
* Currently we can't call ioremap here because
* SoC detection won't work until after init_early.
*/
scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
BUG_ON(!scu_base);
ncores = scu_get_core_count(scu_base);
} else if (cpu_id == CPU_CORTEX_A15) {
ncores = OMAP5_CORE_COUNT;
}
/* sanity check */
if (ncores > nr_cpu_ids) {
@ -178,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the SCU and wake up the secondary core using
* wakeup_secondary().
*/
scu_enable(scu_base);
if (scu_base)
scu_enable(scu_base);
wakeup_secondary();
}

114
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -33,18 +33,23 @@
#include "omap4-sar-layout.h"
#include "common.h"
#define NR_REG_BANKS 4
#define MAX_IRQS 128
#define MAX_NR_REG_BANKS 5
#define MAX_IRQS 160
#define WKG_MASK_ALL 0x00000000
#define WKG_UNMASK_ALL 0xffffffff
#define CPU_ENA_OFFSET 0x400
#define CPU0_ID 0x0
#define CPU1_ID 0x1
#define OMAP4_NR_BANKS 4
#define OMAP4_NR_IRQS 128
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[NR_IRQS];
static unsigned int irq_banks = MAX_NR_REG_BANKS;
static unsigned int max_irqs = MAX_IRQS;
static unsigned int omap_secure_apis;
/*
* Static helper functions.
@ -146,13 +151,13 @@ static void wakeupgen_unmask(struct irq_data *d)
}
#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
for (i = 0; i < irq_banks; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
@ -160,7 +165,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
for (i = 0; i < irq_banks; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
@ -168,7 +173,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
for (i = 0; i < irq_banks; i++)
wakeupgen_writel(reg, i, cpu);
}
@ -196,25 +201,14 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
#endif
#ifdef CONFIG_CPU_PM
/*
* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
* ROM code. WakeupGen IP is integrated along with GIC to manage the
* interrupt wakeups from CPU low power states. It manages
* masking/unmasking of Shared peripheral interrupts(SPI). So the
* interrupt enable/disable control should be in sync and consistent
* at WakeupGen and GIC so that interrupts are not lost.
*/
static void irq_save_context(void)
static inline void omap4_irq_save_context(void)
{
u32 i, val;
if (omap_rev() == OMAP4430_REV_ES1_0)
return;
if (!sar_base)
sar_base = omap4_get_sar_ram_base();
for (i = 0; i < NR_REG_BANKS; i++) {
for (i = 0; i < irq_banks; i++) {
/* Save the CPUx interrupt mask for IRQ 0 to 127 */
val = wakeupgen_readl(i, 0);
sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
@ -254,6 +248,53 @@ static void irq_save_context(void)
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
}
static inline void omap5_irq_save_context(void)
{
u32 i, val;
for (i = 0; i < irq_banks; i++) {
/* Save the CPUx interrupt mask for IRQ 0 to 159 */
val = wakeupgen_readl(i, 0);
sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
val = wakeupgen_readl(i, 1);
sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
}
/* Save AuxBoot* registers */
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
/* Set the Backup Bit Mask status */
val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
}
/*
* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
* ROM code. WakeupGen IP is integrated along with GIC to manage the
* interrupt wakeups from CPU low power states. It manages
* masking/unmasking of Shared peripheral interrupts(SPI). So the
* interrupt enable/disable control should be in sync and consistent
* at WakeupGen and GIC so that interrupts are not lost.
*/
static void irq_save_context(void)
{
if (!sar_base)
sar_base = omap4_get_sar_ram_base();
if (soc_is_omap54xx())
omap5_irq_save_context();
else
omap4_irq_save_context();
}
/*
@ -262,9 +303,14 @@ static void irq_save_context(void)
static void irq_sar_clear(void)
{
u32 val;
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
u32 offset = SAR_BACKUP_STATUS_OFFSET;
if (soc_is_omap54xx())
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
val = __raw_readl(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
__raw_writel(val, sar_base + offset);
}
/*
@ -336,13 +382,25 @@ static struct notifier_block irq_notifier_block = {
static void __init irq_pm_init(void)
{
cpu_pm_register_notifier(&irq_notifier_block);
/* FIXME: Remove this when MPU OSWR support is added */
if (!soc_is_omap54xx())
cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
{}
#endif
void __iomem *omap_get_wakeupgen_base(void)
{
return wakeupgen_base;
}
int omap_secure_apis_support(void)
{
return omap_secure_apis;
}
/*
* Initialise the wakeupgen module.
*/
@ -358,12 +416,18 @@ int __init omap_wakeupgen_init(void)
}
/* Static mapping, never released */
wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
if (WARN_ON(!wakeupgen_base))
return -ENOMEM;
if (cpu_is_omap44xx()) {
irq_banks = OMAP4_NR_BANKS;
max_irqs = OMAP4_NR_IRQS;
omap_secure_apis = 1;
}
/* Clear all IRQ bitmasks at wakeupGen level */
for (i = 0; i < NR_REG_BANKS; i++) {
for (i = 0; i < irq_banks; i++) {
wakeupgen_writel(0, i, CPU0_ID);
wakeupgen_writel(0, i, CPU1_ID);
}
@ -382,7 +446,7 @@ int __init omap_wakeupgen_init(void)
*/
/* Associate all the IRQs to boot CPU like GIC init does. */
for (i = 0; i < NR_IRQS; i++)
for (i = 0; i < max_irqs; i++)
irq_target_cpu[i] = boot_cpu;
irq_hotplug_init();

14
arch/arm/mach-omap2/omap4-common.c
View File

@ -21,6 +21,8 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <plat/irqs.h>
#include <plat/sram.h>
@ -210,6 +212,18 @@ static int __init omap4_sar_ram_init(void)
}
early_initcall(omap4_sar_ram_init);
static struct of_device_id irq_match[] __initdata = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
{ }
};
void __init omap_gic_of_init(void)
{
omap_wakeupgen_init();
of_irq_init(irq_match);
}
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{

12
arch/arm/mach-omap2/omap4-sar-layout.h
View File

@ -12,7 +12,7 @@
#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
/*
* SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
* SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
*/
#define SAR_BANK1_OFFSET 0x0000
#define SAR_BANK2_OFFSET 0x1000
@ -47,4 +47,14 @@
#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
#endif

2
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -3619,7 +3619,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
} else if (cpu_is_omap44xx()) {
} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;

22
arch/arm/mach-omap2/omap_l3_noc.h
View File

@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
0x200, /* DMM2 */
0x300, /* ABE */
0x400, /* L4CFG */
0x600 /* CLK2 PWR DISC */
0x600, /* CLK2 PWR DISC */
0x0, /* Host CLK1 */
0x900 /* L4 Wakeup */
};
static u32 l3_targ_inst_clk2[] = {
@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
0xE00, /* missing in TRM corresponds to AES2*/
0xC00, /* L4 PER3 */
0xA00, /* L4 PER1*/
0xB00 /* L4 PER2*/
0xB00, /* L4 PER2*/
0x0, /* HOST CLK2 */
0x1800, /* CAL */
0x1700 /* LLI */
};
static u32 l3_targ_inst_clk3[] = {
0x0100 /* EMUSS */
0x0100 /* EMUSS */,
0x0300, /* DEBUGSS_CT_TBR */
0x0 /* HOST CLK3 */
};
static struct l3_masters_data {
@ -110,13 +117,15 @@ static struct l3_masters_data {
{ 0xC8, "USBHOSTFS"}
};
static char *l3_targ_inst_name[L3_MODULES][18] = {
static char *l3_targ_inst_name[L3_MODULES][21] = {
{
"DMM1",
"DMM2",
"ABE",
"L4CFG",
"CLK2 PWR DISC",
"HOST CLK1",
"L4 WAKEUP"
},
{
"CORTEX M3" ,
@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
"L4 PER3",
"L4 PER1",
"L4 PER2",
"HOST CLK2",
"CAL",
"LLI"
},
{
"EMUSS",
"DEBUG SOURCE",
"HOST CLK3"
},
};

2
arch/arm/mach-omap2/prcm-common.h
View File

@ -416,7 +416,7 @@ extern void __iomem *cm_base;
extern void __iomem *cm2_base;
extern void __iomem *prcm_mpu_base;
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
extern void omap_prm_base_init(void);
extern void omap_cm_base_init(void);
#else

2
arch/arm/mach-omap2/prcm.c
View File

@ -160,7 +160,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
if (omap2_globals->prcm_mpu)
prcm_mpu_base = omap2_globals->prcm_mpu;
if (cpu_is_omap44xx()) {
if (cpu_is_omap44xx() || soc_is_omap54xx()) {
omap_prm_base_init();
omap_cm_base_init();
}

5
arch/arm/mach-omap2/timer.c
View File

@ -393,6 +393,11 @@ static void __init omap4_timer_init(void)
OMAP_SYS_TIMER(4)
#endif
#ifdef CONFIG_SOC_OMAP5
OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
OMAP_SYS_TIMER(5)
#endif
/**
* omap_timer_init - build and register timer device with an
* associated timer hwmod

4
arch/arm/plat-omap/Kconfig
View File

@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
select USE_OF
select PROC_DEVICETREE if PROC_FS
help
"Systems based on OMAP2, OMAP3 or OMAP4"
"Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
endchoice
@ -150,7 +150,7 @@ config OMAP_32K_TIMER
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
bool "OMAP3 HS/EMU save and restore for L2 AUX control register"

9
arch/arm/plat-omap/common.c
View File

@ -77,3 +77,12 @@ void __init omap_init_consistent_dma_size(void)
init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
#endif
}
/*
* Stub function for OMAP2 so that common files
* continue to build when custom builds are used
*/
int __weak omap_secure_ram_reserve_memblock(void)
{
return 0;
}

16
arch/arm/plat-omap/counter_32k.c
View File

@ -29,7 +29,10 @@
#include <plat/clock.h>
/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
#define OMAP2_32KSYNCNT_CR_OFF 0x10
#define OMAP2_32KSYNCNT_REV_OFF 0x0
#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
/*
* 32KHz clocksource ... always available, on pretty most chips except
@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
int ret;
/*
* 32k sync Counter register offset is at 0x10
* 32k sync Counter IP register offsets vary between the
* highlander version and the legacy ones.
* The 'SCHEME' bits(30-31) of the revision register is used
* to identify the version.
*/
sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
OMAP2_32KSYNCNT_REV_SCHEME)
sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
else
sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
/*
* 120000 rough estimate from the calculations in

22
arch/arm/plat-omap/include/plat/cpu.h
View File

@ -9,7 +9,7 @@
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -70,6 +70,7 @@ unsigned int omap_rev(void);
* cpu_is_omap443x(): True for OMAP4430
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
* soc_is_omap543x(): True for OMAP5430, OMAP5432
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@ -122,6 +123,7 @@ IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(35xx, 0x35)
IS_OMAP_CLASS(54xx, 0x54)
IS_AM_CLASS(33xx, 0x33)
IS_TI_CLASS(81xx, 0x81)
@ -133,6 +135,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_OMAP_SUBCLASS(447x, 0x447)
IS_OMAP_SUBCLASS(543x, 0x543)
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
@ -156,6 +159,8 @@ IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
#define cpu_is_omap447x() 0
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
@ -291,6 +296,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define cpu_is_omap2430() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap3630() 0
#define soc_is_omap5430() 0
/*
* Whether we have MULTI_OMAP1 or not, we still need to distinguish
@ -371,11 +377,18 @@ IS_OMAP_TYPE(3430, 0x3430)
# define cpu_is_omap447x() is_omap447x()
# endif
# if defined(CONFIG_SOC_OMAP5)
# undef soc_is_omap54xx
# undef soc_is_omap543x
# define soc_is_omap54xx() is_omap54xx()
# define soc_is_omap543x() is_omap543x()
#endif
/* Macros to detect if we have OMAP1 or OMAP2 */
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
cpu_is_omap16xx())
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
cpu_is_omap44xx())
cpu_is_omap44xx() || soc_is_omap54xx())
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
@ -428,9 +441,14 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP447X_CLASS 0x44700044
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
#define OMAP54XX_CLASS 0x54000054
#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
void omap4xxx_check_features(void);

1
arch/arm/plat-omap/include/plat/hardware.h
View File

@ -288,5 +288,6 @@
#include <plat/omap44xx.h>
#include <plat/ti81xx.h>
#include <plat/am33xx.h>
#include <plat/omap54xx.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */

9
arch/arm/plat-omap/include/plat/multi.h
View File

@ -99,4 +99,13 @@
# endif
#endif
#ifdef CONFIG_SOC_OMAP5
# ifdef OMAP_NAME
# undef MULTI_OMAP2
# define MULTI_OMAP2
# else
# define OMAP_NAME omap5
# endif
#endif
#endif /* __PLAT_OMAP_MULTI_H */

5
arch/arm/plat-omap/include/plat/omap-secure.h
View File

@ -3,12 +3,7 @@
#include <linux/types.h>
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
extern int omap_secure_ram_reserve_memblock(void);
#else
static inline void omap_secure_ram_reserve_memblock(void)
{ }
#endif
#ifdef CONFIG_OMAP4_ERRATA_I688
extern int omap_barrier_reserve_memblock(void);

32
arch/arm/plat-omap/include/plat/omap54xx.h Normal file
View File

@ -0,0 +1,32 @@
/*:
* Address mappings and base address for OMAP5 interconnects
* and peripherals.
*
* Copyright (C) 2012 Texas Instruments
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_SOC_OMAP54XX_H
#define __ASM_SOC_OMAP54XX_H
/*
* Please place only base defines here and put the rest in device
* specific headers.
*/
#define L4_54XX_BASE 0x4a000000
#define L4_WK_54XX_BASE 0x4ae00000
#define L4_PER_54XX_BASE 0x48000000
#define L3_54XX_BASE 0x44000000
#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
#define OMAP54XX_CM_CORE_BASE 0x4a008000
#define OMAP54XX_PRM_BASE 0x4ae06000
#define OMAP54XX_PRCM_MPU_BASE 0x48243000
#define OMAP54XX_SCM_BASE 0x4a002000
#define OMAP54XX_CTRL_BASE 0x4a002800
#endif /* __ASM_SOC_OMAP555554XX_H */

10
arch/arm/plat-omap/include/plat/serial.h
View File

@ -63,6 +63,14 @@
/* AM33XX serial port */
#define AM33XX_UART1_BASE 0x44E09000
/* OMAP5 serial ports */
#define OMAP5_UART1_BASE OMAP2_UART1_BASE
#define OMAP5_UART2_BASE OMAP2_UART2_BASE
#define OMAP5_UART3_BASE OMAP4_UART3_BASE
#define OMAP5_UART4_BASE OMAP4_UART4_BASE
#define OMAP5_UART5_BASE 0x48066000
#define OMAP5_UART6_BASE 0x48068000
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
@ -97,6 +105,8 @@
#define TI81XXUART2 82
#define TI81XXUART3 83
#define AM33XXUART1 84
#define OMAP5UART3 OMAP4UART3
#define OMAP5UART4 OMAP4UART4
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */

6
arch/arm/plat-omap/include/plat/uncompress.h
View File

@ -95,6 +95,9 @@ static inline void flush(void)
_DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
OMAP4UART##p)
#define DEBUG_LL_OMAP5(p, mach) \
_DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
OMAP5UART##p)
/* Zoom2/3 shift is different for UART1 and external port */
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@ -177,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_OMAP4(3, omap_4430sdp);
DEBUG_LL_OMAP4(3, omap4_panda);
/* omap5 based boards using UART3 */
DEBUG_LL_OMAP5(3, omap5_sevm);
/* zoom2/3 external uart */
DEBUG_LL_ZOOM(omap_zoom2);
DEBUG_LL_ZOOM(omap_zoom3);

11
arch/arm/plat-omap/sram.c
View File

@ -6,8 +6,8 @@
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
* Copyright (C) 2009-2012 Texas Instruments
* Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -44,6 +44,7 @@
#else
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#endif
#define OMAP5_SRAM_PA 0x40300000
#if defined(CONFIG_ARCH_OMAP2PLUS)
#define SRAM_BOOTLOADER_SZ 0x00
@ -118,6 +119,9 @@ static void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PUB_PA;
omap_sram_size = 0xa000; /* 40K */
} else if (soc_is_omap54xx()) {
omap_sram_start = OMAP5_SRAM_PA;
omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0xe000; /* 56K */
} else if (soc_is_omap54xx()) {
omap_sram_start = OMAP5_SRAM_PA;
omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())