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https://github.com/torvalds/linux.git
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Thumb-2: Implement the unified boot code
This patch adds the ARM/Thumb-2 unified support for the arch/arm/boot/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas
parent
07f33a035d
commit
0e056f20f1
@ -140,7 +140,8 @@ start:
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tst r2, #3 @ not user?
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bne not_angel
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mov r0, #0x17 @ angel_SWIreason_EnterSVC
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swi 0x123456 @ angel_SWI_ARM
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ARM( swi 0x123456 ) @ angel_SWI_ARM
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THUMB( svc 0xab ) @ angel_SWI_THUMB
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not_angel:
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mrs r2, cpsr @ turn off interrupts to
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orr r2, r2, #0xc0 @ prevent angel from running
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@ -161,7 +162,9 @@ not_angel:
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.text
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adr r0, LC0
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ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
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ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} )
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THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, ip} )
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THUMB( ldr sp, [r0, #28] )
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subs r0, r0, r1 @ calculate the delta offset
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@ if delta is zero, we are
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@ -263,22 +266,25 @@ not_relocated: mov r0, #0
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* r6 = processor ID
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* r7 = architecture ID
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* r8 = atags pointer
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* r9-r14 = corrupted
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* r9-r12,r14 = corrupted
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*/
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add r1, r5, r0 @ end of decompressed kernel
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adr r2, reloc_start
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ldr r3, LC1
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add r3, r2, r3
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1: ldmia r2!, {r9 - r14} @ copy relocation code
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stmia r1!, {r9 - r14}
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ldmia r2!, {r9 - r14}
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stmia r1!, {r9 - r14}
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1: ldmia r2!, {r9 - r12, r14} @ copy relocation code
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stmia r1!, {r9 - r12, r14}
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ldmia r2!, {r9 - r12, r14}
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stmia r1!, {r9 - r12, r14}
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cmp r2, r3
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blo 1b
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add sp, r1, #128 @ relocate the stack
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mov sp, r1
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add sp, sp, #128 @ relocate the stack
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bl cache_clean_flush
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add pc, r5, r0 @ call relocation code
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ARM( add pc, r5, r0 ) @ call relocation code
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THUMB( add r12, r5, r0 )
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THUMB( mov pc, r12 ) @ call relocation code
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/*
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* We're not in danger of overwriting ourselves. Do this the simple way.
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@ -499,6 +505,7 @@ __arm6_mmu_cache_on:
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mov pc, r12
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__common_mmu_cache_on:
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#ifndef CONFIG_THUMB2_KERNEL
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#ifndef DEBUG
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orr r0, r0, #0x000d @ Write buffer, mmu
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#endif
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@ -510,6 +517,7 @@ __common_mmu_cache_on:
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1: mcr p15, 0, r0, c1, c0, 0 @ load control register
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mrc p15, 0, r0, c1, c0, 0 @ and read it back to
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sub pc, lr, r0, lsr #32 @ properly flush pipeline
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#endif
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/*
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* All code following this line is relocatable. It is relocated by
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@ -523,7 +531,7 @@ __common_mmu_cache_on:
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* r6 = processor ID
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* r7 = architecture ID
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* r8 = atags pointer
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* r9-r14 = corrupted
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* r9-r12,r14 = corrupted
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*/
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.align 5
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reloc_start: add r9, r5, r0
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@ -532,13 +540,14 @@ reloc_start: add r9, r5, r0
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mov r1, r4
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1:
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.rept 4
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ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
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stmia r1!, {r0, r2, r3, r10 - r14}
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ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel
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stmia r1!, {r0, r2, r3, r10 - r12, r14}
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.endr
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cmp r5, r9
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blo 1b
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add sp, r1, #128 @ relocate the stack
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mov sp, r1
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add sp, sp, #128 @ relocate the stack
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debug_reloc_end
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call_kernel: bl cache_clean_flush
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@ -572,7 +581,9 @@ call_cache_fn: adr r12, proc_types
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ldr r2, [r12, #4] @ get mask
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eor r1, r1, r6 @ (real ^ match)
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tst r1, r2 @ & mask
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addeq pc, r12, r3 @ call cache function
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ARM( addeq pc, r12, r3 ) @ call cache function
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THUMB( addeq r12, r3 )
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THUMB( moveq pc, r12 ) @ call cache function
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add r12, r12, #4*5
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b 1b
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@ -595,9 +606,10 @@ call_cache_fn: adr r12, proc_types
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proc_types:
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.word 0x41560600 @ ARM6/610
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.word 0xffffffe0
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b __arm6_mmu_cache_off @ works, but slow
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b __arm6_mmu_cache_off
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W(b) __arm6_mmu_cache_off @ works, but slow
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W(b) __arm6_mmu_cache_off
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mov pc, lr
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THUMB( nop )
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@ b __arm6_mmu_cache_on @ untested
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@ b __arm6_mmu_cache_off
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@ b __armv3_mmu_cache_flush
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@ -605,76 +617,84 @@ proc_types:
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.word 0x00000000 @ old ARM ID
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.word 0x0000f000
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mov pc, lr
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THUMB( nop )
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mov pc, lr
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THUMB( nop )
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mov pc, lr
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THUMB( nop )
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.word 0x41007000 @ ARM7/710
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.word 0xfff8fe00
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b __arm7_mmu_cache_off
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b __arm7_mmu_cache_off
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W(b) __arm7_mmu_cache_off
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W(b) __arm7_mmu_cache_off
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mov pc, lr
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THUMB( nop )
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.word 0x41807200 @ ARM720T (writethrough)
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.word 0xffffff00
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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mov pc, lr
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THUMB( nop )
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.word 0x41007400 @ ARM74x
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.word 0xff00ff00
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b __armv3_mpu_cache_on
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b __armv3_mpu_cache_off
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b __armv3_mpu_cache_flush
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W(b) __armv3_mpu_cache_on
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W(b) __armv3_mpu_cache_off
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W(b) __armv3_mpu_cache_flush
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.word 0x41009400 @ ARM94x
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.word 0xff00ff00
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b __armv4_mpu_cache_on
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b __armv4_mpu_cache_off
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b __armv4_mpu_cache_flush
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W(b) __armv4_mpu_cache_on
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W(b) __armv4_mpu_cache_off
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W(b) __armv4_mpu_cache_flush
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.word 0x00007000 @ ARM7 IDs
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.word 0x0000f000
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mov pc, lr
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THUMB( nop )
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mov pc, lr
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THUMB( nop )
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mov pc, lr
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THUMB( nop )
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@ Everything from here on will be the new ID system.
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.word 0x4401a100 @ sa110 / sa1100
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.word 0xffffffe0
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x6901b110 @ sa1110
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.word 0xfffffff0
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x56056930
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.word 0xff0ffff0 @ PXA935
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x56158000 @ PXA168
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.word 0xfffff000
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv5tej_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv5tej_mmu_cache_flush
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.word 0x56056930
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.word 0xff0ffff0 @ PXA935
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x56050000 @ Feroceon
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.word 0xff0f0000
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv5tej_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv5tej_mmu_cache_flush
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#ifdef CONFIG_CPU_FEROCEON_OLD_ID
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/* this conflicts with the standard ARMv5TE entry */
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@ -687,47 +707,50 @@ proc_types:
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.word 0x66015261 @ FA526
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.word 0xff01fff1
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b __fa526_cache_on
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b __armv4_mmu_cache_off
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b __fa526_cache_flush
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W(b) __fa526_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __fa526_cache_flush
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@ These match on the architecture ID
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.word 0x00020000 @ ARMv4T
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.word 0x000f0000
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x00050000 @ ARMv5TE
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.word 0x000f0000
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x00060000 @ ARMv5TEJ
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.word 0x000f0000
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv5tej_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv4_mmu_cache_flush
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.word 0x0007b000 @ ARMv6
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.word 0x000ff000
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv6_mmu_cache_flush
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W(b) __armv4_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv6_mmu_cache_flush
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.word 0x000f0000 @ new CPU Id
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.word 0x000f0000
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b __armv7_mmu_cache_on
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b __armv7_mmu_cache_off
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b __armv7_mmu_cache_flush
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W(b) __armv7_mmu_cache_on
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W(b) __armv7_mmu_cache_off
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W(b) __armv7_mmu_cache_flush
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.word 0 @ unrecognised type
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.word 0
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mov pc, lr
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THUMB( nop )
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mov pc, lr
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THUMB( nop )
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mov pc, lr
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THUMB( nop )
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.size proc_types, . - proc_types
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@ -854,7 +877,7 @@ __armv7_mmu_cache_flush:
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b iflush
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hierarchical:
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mcr p15, 0, r10, c7, c10, 5 @ DMB
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stmfd sp!, {r0-r5, r7, r9, r11}
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stmfd sp!, {r0-r7, r9-r11}
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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@ -879,8 +902,12 @@ loop1:
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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THUMB( lsl r6, r7, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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@ -891,7 +918,7 @@ skip:
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cmp r3, r10
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bgt loop1
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finished:
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ldmfd sp!, {r0-r5, r7, r9, r11}
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ldmfd sp!, {r0-r7, r9-r11}
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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iflush:
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@ -925,9 +952,13 @@ __armv4_mmu_cache_flush:
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mov r11, #8
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mov r11, r11, lsl r3 @ cache line size in bytes
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no_cache_id:
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bic r1, pc, #63 @ align to longest cache line
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mov r1, pc
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bic r1, r1, #63 @ align to longest cache line
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add r2, r1, r2
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1: ldr r3, [r1], r11 @ s/w flush D cache
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1:
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ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
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THUMB( ldr r3, [r1] ) @ s/w flush D cache
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THUMB( add r1, r1, r11 )
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teq r1, r2
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bne 1b
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