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ARC: Add perf support for ARC700 cores
This adds basic perf support for ARC700 cores. Most PERF_COUNT_HW* events are supported now. Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Mischa Jonker
Vineet Gupta
parent
9c8e612d9d
commit
0dd450fe13
@ -67,5 +67,9 @@
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reg = <1>;
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};
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};
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arcpmu0: pmu {
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compatible = "snps,arc700-pmu";
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};
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};
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};
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@ -1,5 +1,7 @@
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/*
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* Copyright (C) 2011-2012 Synopsys, Inc. (www.synopsys.com)
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* Linux performance counter support for ARC
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*
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* Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -10,4 +12,204 @@
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#ifndef __ASM_PERF_EVENT_H
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#define __ASM_PERF_EVENT_H
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/* real maximum varies per CPU, this is the maximum supported by the driver */
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#define ARC_PMU_MAX_HWEVENTS 64
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#define ARC_REG_CC_BUILD 0xF6
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#define ARC_REG_CC_INDEX 0x240
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#define ARC_REG_CC_NAME0 0x241
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#define ARC_REG_CC_NAME1 0x242
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#define ARC_REG_PCT_BUILD 0xF5
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#define ARC_REG_PCT_COUNTL 0x250
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#define ARC_REG_PCT_COUNTH 0x251
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#define ARC_REG_PCT_SNAPL 0x252
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#define ARC_REG_PCT_SNAPH 0x253
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#define ARC_REG_PCT_CONFIG 0x254
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#define ARC_REG_PCT_CONTROL 0x255
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#define ARC_REG_PCT_INDEX 0x256
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#define ARC_REG_PCT_CONTROL_CC (1 << 16) /* clear counts */
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#define ARC_REG_PCT_CONTROL_SN (1 << 17) /* snapshot */
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struct arc_reg_pct_build {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int m:8, c:8, r:6, s:2, v:8;
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#else
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unsigned int v:8, s:2, r:6, c:8, m:8;
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#endif
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};
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struct arc_reg_cc_build {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int c:16, r:8, v:8;
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#else
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unsigned int v:8, r:8, c:16;
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#endif
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};
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#define PERF_COUNT_ARC_DCLM (PERF_COUNT_HW_MAX + 0)
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#define PERF_COUNT_ARC_DCSM (PERF_COUNT_HW_MAX + 1)
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#define PERF_COUNT_ARC_ICM (PERF_COUNT_HW_MAX + 2)
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#define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3)
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#define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4)
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#define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5)
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#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 6)
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/*
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* The "generalized" performance events seem to really be a copy
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* of the available events on x86 processors; the mapping to ARC
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* events is not always possible 1-to-1. Fortunately, there doesn't
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* seem to be an exact definition for these events, so we can cheat
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* a bit where necessary.
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*
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* In particular, the following PERF events may behave a bit differently
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* compared to other architectures:
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*
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* PERF_COUNT_HW_CPU_CYCLES
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* Cycles not in halted state
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*
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* PERF_COUNT_HW_REF_CPU_CYCLES
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* Reference cycles not in halted state, same as PERF_COUNT_HW_CPU_CYCLES
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* for now as we don't do Dynamic Voltage/Frequency Scaling (yet)
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*
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* PERF_COUNT_HW_BUS_CYCLES
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* Unclear what this means, Intel uses 0x013c, which according to
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* their datasheet means "unhalted reference cycles". It sounds similar
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* to PERF_COUNT_HW_REF_CPU_CYCLES, and we use the same counter for it.
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*
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* PERF_COUNT_HW_STALLED_CYCLES_BACKEND
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* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
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* The ARC 700 can either measure stalls per pipeline stage, or all stalls
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* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
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* and all pipeline flushes (e.g. caused by mispredicts, etc.) to
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* STALLED_CYCLES_FRONTEND.
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*
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* We could start multiple performance counters and combine everything
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* afterwards, but that makes it complicated.
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*
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* Note that I$ cache misses aren't counted by either of the two!
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*/
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static const char * const arc_pmu_ev_hw_map[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = "crun",
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[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
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[PERF_COUNT_HW_BUS_CYCLES] = "crun",
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[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail",
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp",
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
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[PERF_COUNT_ARC_DCLM] = "dclm",
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[PERF_COUNT_ARC_DCSM] = "dcsm",
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[PERF_COUNT_ARC_ICM] = "icm",
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[PERF_COUNT_ARC_BPOK] = "bpok",
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[PERF_COUNT_ARC_EDTLB] = "edtlb",
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[PERF_COUNT_ARC_EITLB] = "eitlb",
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};
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xffff
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static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
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[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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#endif /* __ASM_PERF_EVENT_H */
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@ -19,6 +19,7 @@ obj-$(CONFIG_KPROBES) += kprobes.o
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obj-$(CONFIG_ARC_MISALIGN_ACCESS) += unaligned.o
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obj-$(CONFIG_KGDB) += kgdb.o
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obj-$(CONFIG_ARC_METAWARE_HLINK) += arc_hostlink.o
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obj-$(CONFIG_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_ARC_FPU_SAVE_RESTORE) += fpu.o
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CFLAGS_fpu.o += -mdpfp
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322
arch/arc/kernel/perf_event.c
Normal file
322
arch/arc/kernel/perf_event.c
Normal file
@ -0,0 +1,322 @@
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/*
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* Linux performance counter support for ARC700 series
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*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This code is inspired by the perf support of various other architectures.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <asm/arcregs.h>
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struct arc_pmu {
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struct pmu pmu;
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int counter_size; /* in bits */
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int n_counters;
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unsigned long used_mask[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS)];
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int ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
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};
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/* read counter #idx; note that counter# != event# on ARC! */
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static uint64_t arc_pmu_read_counter(int idx)
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{
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uint32_t tmp;
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uint64_t result;
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/*
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* ARC supports making 'snapshots' of the counters, so we don't
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* need to care about counters wrapping to 0 underneath our feet
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*/
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
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result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
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result |= read_aux_reg(ARC_REG_PCT_SNAPL);
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return result;
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}
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static void arc_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
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uint64_t prev_raw_count, new_raw_count;
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int64_t delta;
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do {
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = arc_pmu_read_counter(idx);
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} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count);
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delta = (new_raw_count - prev_raw_count) &
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((1ULL << arc_pmu->counter_size) - 1ULL);
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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}
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static void arc_pmu_read(struct perf_event *event)
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{
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arc_perf_event_update(event, &event->hw, event->hw.idx);
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}
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static int arc_pmu_cache_event(u64 config)
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{
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unsigned int cache_type, cache_op, cache_result;
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int ret;
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cache_type = (config >> 0) & 0xff;
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cache_op = (config >> 8) & 0xff;
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cache_result = (config >> 16) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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if (cache_type >= PERF_COUNT_HW_CACHE_OP_MAX)
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return -EINVAL;
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if (cache_type >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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return ret;
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}
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/* initializes hw_perf_event structure if event is supported */
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static int arc_pmu_event_init(struct perf_event *event)
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{
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struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
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struct hw_perf_event *hwc = &event->hw;
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int ret;
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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if (event->attr.config >= PERF_COUNT_HW_MAX)
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return -ENOENT;
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if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
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return -ENOENT;
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hwc->config = arc_pmu->ev_hw_idx[event->attr.config];
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pr_debug("initializing event %d with cfg %d\n",
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(int) event->attr.config, (int) hwc->config);
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return 0;
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case PERF_TYPE_HW_CACHE:
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ret = arc_pmu_cache_event(event->attr.config);
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if (ret < 0)
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return ret;
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hwc->config = arc_pmu->ev_hw_idx[ret];
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return 0;
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default:
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return -ENOENT;
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}
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}
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/* starts all counters */
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static void arc_pmu_enable(struct pmu *pmu)
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{
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uint32_t tmp;
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
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}
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/* stops all counters */
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static void arc_pmu_disable(struct pmu *pmu)
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{
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uint32_t tmp;
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
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}
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/*
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* Assigns hardware counter to hardware condition.
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* Note that there is no separate start/stop mechanism;
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* stopping is achieved by assigning the 'never' condition
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*/
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static void arc_pmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (WARN_ON_ONCE(idx == -1))
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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event->hw.state = 0;
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/* enable ARC pmu here */
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);
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}
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static void arc_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (!(event->hw.state & PERF_HES_STOPPED)) {
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/* stop ARC pmu here */
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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/* condition code #0 is always "never" */
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write_aux_reg(ARC_REG_PCT_CONFIG, 0);
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event->hw.state |= PERF_HES_STOPPED;
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}
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if ((flags & PERF_EF_UPDATE) &&
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!(event->hw.state & PERF_HES_UPTODATE)) {
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arc_perf_event_update(event, &event->hw, idx);
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event->hw.state |= PERF_HES_UPTODATE;
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}
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}
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static void arc_pmu_del(struct perf_event *event, int flags)
|
||||
{
|
||||
struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
|
||||
|
||||
arc_pmu_stop(event, PERF_EF_UPDATE);
|
||||
__clear_bit(event->hw.idx, arc_pmu->used_mask);
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
}
|
||||
|
||||
/* allocate hardware counter and optionally start counting */
|
||||
static int arc_pmu_add(struct perf_event *event, int flags)
|
||||
{
|
||||
struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (__test_and_set_bit(idx, arc_pmu->used_mask)) {
|
||||
idx = find_first_zero_bit(arc_pmu->used_mask,
|
||||
arc_pmu->n_counters);
|
||||
if (idx == arc_pmu->n_counters)
|
||||
return -EAGAIN;
|
||||
|
||||
__set_bit(idx, arc_pmu->used_mask);
|
||||
hwc->idx = idx;
|
||||
}
|
||||
|
||||
write_aux_reg(ARC_REG_PCT_INDEX, idx);
|
||||
write_aux_reg(ARC_REG_PCT_CONFIG, 0);
|
||||
write_aux_reg(ARC_REG_PCT_COUNTL, 0);
|
||||
write_aux_reg(ARC_REG_PCT_COUNTH, 0);
|
||||
local64_set(&hwc->prev_count, 0);
|
||||
|
||||
hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
|
||||
if (flags & PERF_EF_START)
|
||||
arc_pmu_start(event, PERF_EF_RELOAD);
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int arc_pmu_device_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct arc_pmu *arc_pmu;
|
||||
struct arc_reg_pct_build pct_bcr;
|
||||
struct arc_reg_cc_build cc_bcr;
|
||||
int i, j, ret;
|
||||
|
||||
union cc_name {
|
||||
struct {
|
||||
uint32_t word0, word1;
|
||||
char sentinel;
|
||||
} indiv;
|
||||
char str[9];
|
||||
} cc_name;
|
||||
|
||||
|
||||
READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
|
||||
if (!pct_bcr.v) {
|
||||
pr_err("This core does not have performance counters!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu),
|
||||
GFP_KERNEL);
|
||||
if (!arc_pmu)
|
||||
return -ENOMEM;
|
||||
|
||||
arc_pmu->n_counters = pct_bcr.c;
|
||||
BUG_ON(arc_pmu->n_counters > ARC_PMU_MAX_HWEVENTS);
|
||||
|
||||
arc_pmu->counter_size = 32 + (pct_bcr.s << 4);
|
||||
pr_info("ARC PMU found with %d counters of size %d bits\n",
|
||||
arc_pmu->n_counters, arc_pmu->counter_size);
|
||||
|
||||
READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
|
||||
|
||||
if (!cc_bcr.v)
|
||||
pr_err("Strange! Performance counters exist, but no countable conditions?\n");
|
||||
|
||||
pr_info("ARC PMU has %d countable conditions\n", cc_bcr.c);
|
||||
|
||||
cc_name.str[8] = 0;
|
||||
for (i = 0; i < PERF_COUNT_HW_MAX; i++)
|
||||
arc_pmu->ev_hw_idx[i] = -1;
|
||||
|
||||
for (j = 0; j < cc_bcr.c; j++) {
|
||||
write_aux_reg(ARC_REG_CC_INDEX, j);
|
||||
cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
|
||||
cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
|
||||
for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
|
||||
if (arc_pmu_ev_hw_map[i] &&
|
||||
!strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
|
||||
strlen(arc_pmu_ev_hw_map[i])) {
|
||||
pr_debug("mapping %d to idx %d with name %s\n",
|
||||
i, j, cc_name.str);
|
||||
arc_pmu->ev_hw_idx[i] = j;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
arc_pmu->pmu = (struct pmu) {
|
||||
.pmu_enable = arc_pmu_enable,
|
||||
.pmu_disable = arc_pmu_disable,
|
||||
.event_init = arc_pmu_event_init,
|
||||
.add = arc_pmu_add,
|
||||
.del = arc_pmu_del,
|
||||
.start = arc_pmu_start,
|
||||
.stop = arc_pmu_stop,
|
||||
.read = arc_pmu_read,
|
||||
};
|
||||
|
||||
ret = perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id arc_pmu_match[] = {
|
||||
{ .compatible = "snps,arc700-pmu" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, arc_pmu_match);
|
||||
#endif
|
||||
|
||||
static struct platform_driver arc_pmu_driver = {
|
||||
.driver = {
|
||||
.name = "arc700-pmu",
|
||||
.of_match_table = of_match_ptr(arc_pmu_match),
|
||||
},
|
||||
.probe = arc_pmu_device_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(arc_pmu_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
|
||||
MODULE_DESCRIPTION("ARC PMU driver");
|
||||
Loading…
Reference in New Issue
Block a user