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IB/qib: Use pcie_set_mps() and pcie_get_mps() to simplify code
Refactor qib_tune_pcie_caps(). Use pcie_get_mps(), pcie_set_mps(), pcie_get_readrq(), and pcie_set_readrq() to simplify the code. The PCI core caches the "PCIe Max Payload Size Supported" in pci_dev->pcie_mpss, so use that instead of pcie_capability_read_word(). Remove the unused val2fld() and fld2val(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
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dcaa73dc34
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0ce0e62f1f
@ -476,30 +476,6 @@ void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
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"pci_enable_device failed after reset: %d\n", r);
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}
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/* code to adjust PCIe capabilities. */
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static int fld2val(int wd, int mask)
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{
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int lsbmask;
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if (!mask)
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return 0;
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wd &= mask;
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lsbmask = mask ^ (mask & (mask - 1));
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wd /= lsbmask;
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return wd;
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}
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static int val2fld(int wd, int mask)
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{
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int lsbmask;
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if (!mask)
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return 0;
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lsbmask = mask ^ (mask & (mask - 1));
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wd *= lsbmask;
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return wd;
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}
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static int qib_pcie_coalesce;
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module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
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@ -584,9 +560,8 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
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{
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int ret = 1; /* Assume the worst */
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struct pci_dev *parent;
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u16 pcaps, pctl, ecaps, ectl;
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int rc_sup, ep_sup;
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int rc_cur, ep_cur;
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u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
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u16 rc_mrrs, ep_mrrs, max_mrrs;
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/* Find out supported and configured values for parent (root) */
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parent = dd->pcidev->bus->self;
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@ -597,38 +572,29 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
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if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
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goto bail;
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pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
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pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl);
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rc_mpss = parent->pcie_mpss;
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rc_mps = ffs(pcie_get_mps(parent)) - 8;
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/* Find out supported and configured values for endpoint (us) */
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pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
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pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
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ep_mpss = dd->pcidev->pcie_mpss;
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ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
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ret = 0;
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/* Find max payload supported by root, endpoint */
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rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
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ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD);
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if (rc_sup > ep_sup)
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rc_sup = ep_sup;
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rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD);
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ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD);
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if (rc_mpss > ep_mpss)
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rc_mpss = ep_mpss;
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/* If Supported greater than limit in module param, limit it */
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if (rc_sup > (qib_pcie_caps & 7))
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rc_sup = qib_pcie_caps & 7;
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if (rc_mpss > (qib_pcie_caps & 7))
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rc_mpss = qib_pcie_caps & 7;
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/* If less than (allowed, supported), bump root payload */
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if (rc_sup > rc_cur) {
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rc_cur = rc_sup;
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pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
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val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
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pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
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if (rc_mpss > rc_mps) {
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rc_mps = rc_mpss;
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pcie_set_mps(parent, 128 << rc_mps);
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}
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/* If less than (allowed, supported), bump endpoint payload */
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if (rc_sup > ep_cur) {
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ep_cur = rc_sup;
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ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
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val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
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pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
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if (rc_mpss > ep_mps) {
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ep_mps = rc_mpss;
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pcie_set_mps(dd->pcidev, 128 << ep_mps);
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}
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/*
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@ -636,23 +602,21 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
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* No field for max supported, but PCIe spec limits it to 4096,
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* which is code '5' (log2(4096) - 7)
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*/
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rc_sup = 5;
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if (rc_sup > ((qib_pcie_caps >> 4) & 7))
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rc_sup = (qib_pcie_caps >> 4) & 7;
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rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ);
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ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ);
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max_mrrs = 5;
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if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
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max_mrrs = (qib_pcie_caps >> 4) & 7;
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if (rc_sup > rc_cur) {
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rc_cur = rc_sup;
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pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
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val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
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pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
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max_mrrs = 128 << max_mrrs;
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rc_mrrs = pcie_get_readrq(parent);
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ep_mrrs = pcie_get_readrq(dd->pcidev);
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if (max_mrrs > rc_mrrs) {
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rc_mrrs = max_mrrs;
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pcie_set_readrq(parent, rc_mrrs);
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}
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if (rc_sup > ep_cur) {
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ep_cur = rc_sup;
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ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
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val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
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pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
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if (max_mrrs > ep_mrrs) {
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ep_mrrs = max_mrrs;
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pcie_set_readrq(dd->pcidev, ep_mrrs);
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}
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bail:
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return ret;
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