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netdev/of/phy: Add MDIO bus multiplexer support.
This patch adds a somewhat generic framework for MDIO bus
multiplexers. It is modeled on the I2C multiplexer.
The multiplexer is needed if there are multiple PHYs with the same
address connected to the same MDIO bus adepter, or if there is
insufficient electrical drive capability for all the connected PHY
devices.
Conceptually it could look something like this:
------------------
| Control Signal |
--------+---------
|
--------------- --------+------
| MDIO MASTER |---| Multiplexer |
--------------- --+-------+----
| |
C C
h h
i i
l l
d d
| |
--------- A B ---------
| | | | | |
| PHY@1 +-------+ +---+ PHY@1 |
| | | | | |
--------- | | ---------
--------- | | ---------
| | | | | |
| PHY@2 +-------+ +---+ PHY@2 |
| | | |
--------- ---------
This framework configures the bus topology from device tree data. The
mechanics of switching the multiplexer is left to device specific
drivers.
The follow-on patch contains a multiplexer driven by GPIO lines.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David Daney
David S. Miller
parent
2510602200
commit
0ca2997d14
136
Documentation/devicetree/bindings/net/mdio-mux.txt
Normal file
136
Documentation/devicetree/bindings/net/mdio-mux.txt
Normal file
@ -0,0 +1,136 @@
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Common MDIO bus multiplexer/switch properties.
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An MDIO bus multiplexer/switch will have several child busses that are
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numbered uniquely in a device dependent manner. The nodes for an MDIO
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bus multiplexer/switch will have one child node for each child bus.
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Required properties:
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- mdio-parent-bus : phandle to the parent MDIO bus.
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- #address-cells = <1>;
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- #size-cells = <0>;
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Optional properties:
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- Other properties specific to the multiplexer/switch hardware.
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Required properties for child nodes:
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- #address-cells = <1>;
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- #size-cells = <0>;
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- reg : The sub-bus number.
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Example :
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/* The parent MDIO bus. */
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smi1: mdio@1180000001900 {
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compatible = "cavium,octeon-3860-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11800 0x00001900 0x0 0x40>;
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};
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/*
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An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
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pair of GPIO lines. Child busses 2 and 3 populated with 4
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PHYs each.
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*/
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mdio-mux {
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compatible = "mdio-mux-gpio";
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gpios = <&gpio1 3 0>, <&gpio1 4 0>;
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mdio-parent-bus = <&smi1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy11: ethernet-phy@1 {
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reg = <1>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy12: ethernet-phy@2 {
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reg = <2>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy13: ethernet-phy@3 {
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reg = <3>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy14: ethernet-phy@4 {
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reg = <4>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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};
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mdio@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy21: ethernet-phy@1 {
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reg = <1>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy22: ethernet-phy@2 {
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reg = <2>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy23: ethernet-phy@3 {
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reg = <3>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy24: ethernet-phy@4 {
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reg = <4>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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};
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};
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@ -135,6 +135,15 @@ config MDIO_OCTEON
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If in doubt, say Y.
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config MDIO_BUS_MUX
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tristate
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depends on OF_MDIO
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help
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This module provides a driver framework for MDIO bus
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multiplexers which connect one of several child MDIO busses
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to a parent bus. Switching between child busses is done by
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device specific drivers.
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endif # PHYLIB
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config MICREL_KS8995MA
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@ -25,3 +25,4 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
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obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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obj-$(CONFIG_AMD_PHY) += amd.o
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obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
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192
drivers/net/phy/mdio-mux.c
Normal file
192
drivers/net/phy/mdio-mux.c
Normal file
@ -0,0 +1,192 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/mdio-mux.h>
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#include <linux/of_mdio.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#define DRV_VERSION "1.0"
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#define DRV_DESCRIPTION "MDIO bus multiplexer driver"
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struct mdio_mux_child_bus;
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struct mdio_mux_parent_bus {
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struct mii_bus *mii_bus;
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int current_child;
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int parent_id;
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void *switch_data;
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int (*switch_fn)(int current_child, int desired_child, void *data);
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/* List of our children linked through their next fields. */
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struct mdio_mux_child_bus *children;
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};
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struct mdio_mux_child_bus {
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struct mii_bus *mii_bus;
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struct mdio_mux_parent_bus *parent;
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struct mdio_mux_child_bus *next;
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int bus_number;
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int phy_irq[PHY_MAX_ADDR];
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};
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/*
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* The parent bus' lock is used to order access to the switch_fn.
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*/
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static int mdio_mux_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct mdio_mux_child_bus *cb = bus->priv;
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struct mdio_mux_parent_bus *pb = cb->parent;
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int r;
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mutex_lock(&pb->mii_bus->mdio_lock);
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r = pb->switch_fn(pb->current_child, cb->bus_number, pb->switch_data);
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if (r)
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goto out;
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pb->current_child = cb->bus_number;
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r = pb->mii_bus->read(pb->mii_bus, phy_id, regnum);
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out:
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mutex_unlock(&pb->mii_bus->mdio_lock);
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return r;
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}
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/*
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* The parent bus' lock is used to order access to the switch_fn.
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*/
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static int mdio_mux_write(struct mii_bus *bus, int phy_id,
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int regnum, u16 val)
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{
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struct mdio_mux_child_bus *cb = bus->priv;
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struct mdio_mux_parent_bus *pb = cb->parent;
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int r;
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mutex_lock(&pb->mii_bus->mdio_lock);
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r = pb->switch_fn(pb->current_child, cb->bus_number, pb->switch_data);
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if (r)
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goto out;
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pb->current_child = cb->bus_number;
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r = pb->mii_bus->write(pb->mii_bus, phy_id, regnum, val);
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out:
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mutex_unlock(&pb->mii_bus->mdio_lock);
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return r;
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}
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static int parent_count;
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int mdio_mux_init(struct device *dev,
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int (*switch_fn)(int cur, int desired, void *data),
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void **mux_handle,
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void *data)
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{
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struct device_node *parent_bus_node;
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struct device_node *child_bus_node;
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int r, ret_val;
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struct mii_bus *parent_bus;
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struct mdio_mux_parent_bus *pb;
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struct mdio_mux_child_bus *cb;
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if (!dev->of_node)
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return -ENODEV;
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parent_bus_node = of_parse_phandle(dev->of_node, "mdio-parent-bus", 0);
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if (!parent_bus_node)
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return -ENODEV;
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parent_bus = of_mdio_find_bus(parent_bus_node);
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if (parent_bus == NULL) {
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ret_val = -EPROBE_DEFER;
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goto err_parent_bus;
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}
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pb = devm_kzalloc(dev, sizeof(*pb), GFP_KERNEL);
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if (pb == NULL) {
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ret_val = -ENOMEM;
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goto err_parent_bus;
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}
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pb->switch_data = data;
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pb->switch_fn = switch_fn;
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pb->current_child = -1;
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pb->parent_id = parent_count++;
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pb->mii_bus = parent_bus;
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ret_val = -ENODEV;
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for_each_child_of_node(dev->of_node, child_bus_node) {
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u32 v;
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r = of_property_read_u32(child_bus_node, "reg", &v);
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if (r)
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continue;
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cb = devm_kzalloc(dev, sizeof(*cb), GFP_KERNEL);
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if (cb == NULL) {
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dev_err(dev,
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"Error: Failed to allocate memory for child\n");
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ret_val = -ENOMEM;
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break;
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}
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cb->bus_number = v;
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cb->parent = pb;
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cb->mii_bus = mdiobus_alloc();
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cb->mii_bus->priv = cb;
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cb->mii_bus->irq = cb->phy_irq;
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cb->mii_bus->name = "mdio_mux";
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snprintf(cb->mii_bus->id, MII_BUS_ID_SIZE, "%x.%x",
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pb->parent_id, v);
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cb->mii_bus->parent = dev;
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cb->mii_bus->read = mdio_mux_read;
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cb->mii_bus->write = mdio_mux_write;
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r = of_mdiobus_register(cb->mii_bus, child_bus_node);
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if (r) {
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mdiobus_free(cb->mii_bus);
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devm_kfree(dev, cb);
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} else {
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of_node_get(child_bus_node);
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cb->next = pb->children;
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pb->children = cb;
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}
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}
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if (pb->children) {
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*mux_handle = pb;
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dev_info(dev, "Version " DRV_VERSION "\n");
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return 0;
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}
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err_parent_bus:
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of_node_put(parent_bus_node);
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return ret_val;
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}
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EXPORT_SYMBOL_GPL(mdio_mux_init);
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void mdio_mux_uninit(void *mux_handle)
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{
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struct mdio_mux_parent_bus *pb = mux_handle;
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struct mdio_mux_child_bus *cb = pb->children;
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while (cb) {
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mdiobus_unregister(cb->mii_bus);
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mdiobus_free(cb->mii_bus);
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cb = cb->next;
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}
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}
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EXPORT_SYMBOL_GPL(mdio_mux_uninit);
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MODULE_DESCRIPTION(DRV_DESCRIPTION);
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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21
include/linux/mdio-mux.h
Normal file
21
include/linux/mdio-mux.h
Normal file
@ -0,0 +1,21 @@
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/*
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* MDIO bus multiplexer framwork.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#ifndef __LINUX_MDIO_MUX_H
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#define __LINUX_MDIO_MUX_H
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#include <linux/device.h>
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int mdio_mux_init(struct device *dev,
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int (*switch_fn) (int cur, int desired, void *data),
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void **mux_handle,
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void *data);
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void mdio_mux_uninit(void *mux_handle);
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#endif /* __LINUX_MDIO_MUX_H */
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